mirror of https://github.com/VLSIDA/OpenRAM.git
Mirror port 1 column decoder in X and Y
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@ -724,7 +724,7 @@ class bank(design.design):
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for port in self.all_ports:
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for port in self.all_ports:
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if port%2 == 1:
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if port%2 == 1:
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mirror = "MY"
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mirror = "XY"
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else:
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else:
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mirror = "R0"
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mirror = "R0"
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self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror)
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self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror)
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