mirror of https://github.com/VLSIDA/OpenRAM.git
Supply to M3 for bank select logic
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@ -221,6 +221,32 @@ class bank_select(design.design):
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width=inv_inst.rx() - out_pin.lx(),
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width=inv_inst.rx() - out_pin.lx(),
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height=out_pin.height())
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height=out_pin.height())
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# Find the x offsets for where the vias/pins should be placed
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a_xoffset = self.logic_inst[0].lx()
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b_xoffset = self.inv_inst[0].lx()
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for num in range(self.num_control_lines):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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supply_pin = self.inv_inst[num].get_pin(n)
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supply_offset = supply_pin.ll().scale(0,1)
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self.add_rect(layer="metal1",
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offset=supply_offset,
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width=self.width)
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# Add pins in two locations
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for xoffset in [a_xoffset, b_xoffset]:
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pin_pos = vector(xoffset, supply_pin.cy())
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pin_pos,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos,
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rotate=90)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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# Add vdd/gnd supply rails
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# Add vdd/gnd supply rails
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gnd_pin = inv_inst.get_pin("gnd")
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gnd_pin = inv_inst.get_pin("gnd")
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left_gnd_pos = vector(0, gnd_pin.cy())
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left_gnd_pos = vector(0, gnd_pin.cy())
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