luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Flatten bug fixed in Magic so don't flatten routes.

This commit is contained in:
mrg 2021-01-12 16:20:03 -08:00
parent 2101d89646
commit 6f5b7c0264
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
compiler/sram/sram_1bank.py
View File

@ -11,6 +11,7 @@ from contact import m2_via
from channel_route import channel_route from channel_route import channel_route
from signal_escape_router import signal_escape_router as router from signal_escape_router import signal_escape_router as router
from globals import OPTS from globals import OPTS
import debug
class sram_1bank(sram_base): class sram_1bank(sram_base):
@ -436,9 +437,9 @@ class sram_1bank(sram_base):
if add_routes: if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of isntances
# with no active devices. # with no active devices.
# self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
# self.connect_inst([]) self.connect_inst([])
self.add_flat_inst(cr.name, cr) #self.add_flat_inst(cr.name, cr)
else: else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
else: else:
@ -451,9 +452,9 @@ class sram_1bank(sram_base):
if add_routes: if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of isntances
# with no active devices. # with no active devices.
# self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
# self.connect_inst([]) self.connect_inst([])
self.add_flat_inst(cr.name, cr) #self.add_flat_inst(cr.name, cr)
else: else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap