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Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail.

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This commit is contained in:
Michael Timothy Grimes
2018-10-08 06:34:36 -07:00
parent 7b4e001885
commit 6ef1a3c755
9 changed files with 217 additions and 420 deletions
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compiler/tests/20_psram_1bank_test.py
+3 -3
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@@ -11,7 +11,7 @@ import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class sram_1bank_test(openram_test):
def runTest(self):
@@ -40,7 +40,7 @@ class sram_1bank_test(openram_test):
debug.info(1, "Single bank two way column mux with control logic")
a = sram(c, "sram2")
self.local_check(a, final_verification=True)
"""
c.num_words=64
c.words_per_row=4
debug.info(1, "Single bank, four way column mux with control logic")
@@ -69,7 +69,7 @@ class sram_1bank_test(openram_test):
debug.info(1, "Single bank, no column mux with control logic")
a = sram(c, "sram1")
self.local_check(a, final_verification=True)
"""
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 2
OPTS.num_r_ports = 2
compiler/tests/22_hspice_psram_func_test.py
+5 -4
View File
@@ -38,8 +38,8 @@ class psram_func_test(openram_test):
c.words_per_row=2
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 2
OPTS.num_r_ports = 4
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
s = sram(c, name="sram1")
@@ -49,9 +49,10 @@ class psram_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(success,error) = f.multiport_run()
f.num_cycles = 5
(fail,error) = f.run()
self.assertTrue(not success,error)
self.assertTrue(fail,error)
globals.end_openram()
compiler/tests/22_hspice_sram_func_test.py
+3 -2
View File
@@ -41,9 +41,10 @@ class sram_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(success, error) = f.run()
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(not success,error)
self.assertTrue(fail,error)
globals.end_openram()
compiler/tests/22_ngspice_psram_func_test.py
+5 -4
View File
@@ -38,8 +38,8 @@ class psram_func_test(openram_test):
c.words_per_row=2
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 2
OPTS.num_r_ports = 4
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
s = sram(c, name="sram1")
@@ -49,9 +49,10 @@ class psram_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(success,error) = f.multiport_run()
f.num_cycles = 5
(fail,error) = f.run()
self.assertTrue(not success,error)
self.assertTrue(fail,error)
globals.end_openram()
compiler/tests/22_ngspice_sram_func_test.py
+3 -2
View File
@@ -41,9 +41,10 @@ class sram_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(success, error) = f.run()
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(not success,error)
self.assertTrue(fail,error)
globals.end_openram()