mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 08:27:11 +02:00
Merge branch 'dev' into laptop_checkpoint
This commit is contained in:
Jesse Cirimelli-Low
+10
-18
@@ -329,13 +329,13 @@ class bank(design.design):
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self.input_control_signals = []
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port_num = 0
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for port in range(OPTS.num_rw_ports):
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self.input_control_signals.append(["s_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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self.input_control_signals.append(["p_en_bar{}".format(port_num), "s_en{}".format(port_num), "w_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_w_ports):
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self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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self.input_control_signals.append(["p_en_bar{}".format(port_num), "w_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_r_ports):
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self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
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self.input_control_signals.append(["p_en_bar{}".format(port_num), "s_en{}".format(port_num)])
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port_num += 1
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# Number of control lines in the bus for each port
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@@ -530,13 +530,16 @@ class bank(design.design):
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height=self.dff.height)
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elif self.col_addr_size == 2:
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self.column_decoder = factory.create(module_type="hierarchical_predecode2x4",
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column_decoder=True,
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height=self.dff.height)
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elif self.col_addr_size == 3:
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self.column_decoder = factory.create(module_type="hierarchical_predecode3x8",
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column_decoder=True,
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height=self.dff.height)
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elif self.col_addr_size == 4:
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self.column_decoder = factory.create(module_type="hierarchical_predecode4x16",
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column_decoder=True,
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height=self.dff.height)
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else:
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# No error checking before?
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@@ -692,6 +695,8 @@ class bank(design.design):
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make_pins=(self.num_banks==1),
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pitch=self.m3_pitch)
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self.copy_layout_pin(self.port_address_inst[0], "wl_en", self.prefix + "wl_en0")
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# Port 1
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if len(self.all_ports)==2:
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# The other control bus is routed up to two pitches above the bitcell array
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@@ -707,6 +712,8 @@ class bank(design.design):
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make_pins=(self.num_banks==1),
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pitch=self.m3_pitch)
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self.copy_layout_pin(self.port_address_inst[1], "wl_en", self.prefix + "wl_en1")
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def route_port_data_to_bitcell_array(self, port):
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""" Routing of BL and BR between port data and bitcell array """
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@@ -1055,21 +1062,6 @@ class bank(design.design):
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to_layer="m2",
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offset=control_pos)
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# clk to wordline_driver
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control_signal = self.prefix + "wl_en{}".format(port)
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if port % 2:
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pin_pos = self.port_address_inst[port].get_pin("wl_en").uc()
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control_y_offset = self.bus_pins[port][control_signal].by()
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mid_pos = vector(pin_pos.x, control_y_offset + self.m1_pitch)
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else:
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pin_pos = self.port_address_inst[port].get_pin("wl_en").bc()
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control_y_offset = self.bus_pins[port][control_signal].uy()
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mid_pos = vector(pin_pos.x, control_y_offset - self.m1_pitch)
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control_x_offset = self.bus_pins[port][control_signal].cx()
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control_pos = vector(control_x_offset, mid_pos.y)
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self.add_wire(self.m1_stack, [pin_pos, mid_pos, control_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=control_pos)
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def graph_exclude_precharge(self):
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"""
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@@ -64,7 +64,11 @@ class bitcell_array(bitcell_base_array):
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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# If it is a "core" cell, it could be trimmed for sim time
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if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
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self.trim_insts.add(name)
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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@@ -333,21 +333,19 @@ class control_logic(design.design):
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row += 1
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self.place_gated_clk_buf_row(row)
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row += 1
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self.place_wlen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_wen_row(row)
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height = self.w_en_gate_inst.uy()
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control_center_y = self.w_en_gate_inst.uy()
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_rbl_delay_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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self.place_wlen_row(row)
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row += 1
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self.place_delay(row)
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height = self.delay_inst.uy()
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control_center_y = self.delay_inst.by()
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@@ -11,6 +11,7 @@ from sram_factory import factory
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from vector import vector
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import debug
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from numpy import cumsum
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from tech import layer_properties as layer_props
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class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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@@ -223,11 +224,20 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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new_name = "{0}_{1}".format(base_name, col + col_value)
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self.copy_layout_pin(inst, pin_name, new_name)
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# Add the global word lines
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wl_layer = layer_props.global_bitcell_array.wordline_layer
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for wl_name in self.local_mods[0].get_inputs():
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for local_inst in self.local_insts:
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wl_pin = local_inst.get_pin(wl_name)
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self.add_via_stack_center(from_layer=wl_pin.layer,
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to_layer=wl_layer,
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offset=wl_pin.center())
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left_pin = self.local_insts[0].get_pin(wl_name)
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right_pin = self.local_insts[-1].get_pin(wl_name)
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self.add_layout_pin_segment_center(text=wl_name,
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layer=left_pin.layer,
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layer=wl_layer,
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start=left_pin.lc(),
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end=right_pin.rc())
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@@ -18,19 +18,17 @@ class hierarchical_predecode(design.design):
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"""
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Pre 2x4 and 3x8 and TBD 4x16 decoder shared code.
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"""
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def __init__(self, name, input_number, height=None):
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def __init__(self, name, input_number, column_decoder=False, height=None):
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self.number_of_inputs = input_number
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b = factory.create(module_type=OPTS.bitcell)
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if not height:
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self.cell_height = b.height
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self.column_decoder = False
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else:
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self.cell_height = height
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# If we are pitch matched to the bitcell, it's a predecoder
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# otherwise it's a column decoder (out of pgates)
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self.column_decoder = (height != b.height)
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self.column_decoder = column_decoder
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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super().__init__(name)
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@@ -87,8 +85,14 @@ class hierarchical_predecode(design.design):
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self.bus_layer = layer_props.hierarchical_predecode.bus_layer
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self.bus_directions = layer_props.hierarchical_predecode.bus_directions
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self.bus_pitch = getattr(self, self.bus_layer + "_pitch")
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self.bus_space = layer_props.hierarchical_predecode.bus_space_factor * getattr(self, self.bus_layer + "_space")
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if self.column_decoder:
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# Column decoders may be routed on M2/M3 if there's a write mask
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self.bus_pitch = self.m3_pitch
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self.bus_space = self.m3_space
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else:
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self.bus_pitch = getattr(self, self.bus_layer + "_pitch")
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self.bus_space = getattr(self, self.bus_layer + "_space")
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self.bus_space = layer_props.hierarchical_predecode.bus_space_factor * self.bus_space
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self.input_layer = layer_props.hierarchical_predecode.input_layer
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self.output_layer = layer_props.hierarchical_predecode.output_layer
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self.output_layer_pitch = getattr(self, self.output_layer + "_pitch")
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@@ -114,7 +118,8 @@ class hierarchical_predecode(design.design):
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self.input_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=input_names,
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length=self.height - 2 * self.bus_pitch)
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length=self.height - 2 * self.bus_pitch,
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pitch=self.bus_pitch)
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invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)]
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@@ -123,7 +128,8 @@ class hierarchical_predecode(design.design):
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self.decode_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=decode_names,
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length=self.height - 2 * self.bus_pitch)
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length=self.height - 2 * self.bus_pitch,
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pitch=self.bus_pitch)
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def create_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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@@ -175,10 +181,12 @@ class hierarchical_predecode(design.design):
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mirror=mirror)
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def route(self):
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self.route_input_inverters()
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self.route_output_inverters()
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self.route_inputs_to_rails()
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self.route_and_to_rails()
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self.route_output_and()
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self.route_input_ands()
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self.route_output_ands()
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self.route_vdd_gnd()
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def route_inputs_to_rails(self):
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@@ -210,7 +218,7 @@ class hierarchical_predecode(design.design):
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset])
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def route_output_and(self):
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def route_output_ands(self):
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"""
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Route all conections of the outputs and gates
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"""
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@@ -225,12 +233,40 @@ class hierarchical_predecode(design.design):
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def route_input_inverters(self):
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"""
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Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd]
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Route all conections of the inverter inputs
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"""
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for inv_num in range(self.number_of_inputs):
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in_pin = "in_{}".format(inv_num)
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# route input
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pin = self.inv_inst[inv_num].get_pin("A")
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inv_in_pos = pin.center()
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in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
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self.add_path(self.input_layer, [in_pos, inv_in_pos])
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# Inverter input pin
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=inv_in_pos)
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# Input rail pin position
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via=self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=in_pos,
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directions=self.bus_directions)
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# Create the input pin at this location on the rail
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self.add_layout_pin_rect_center(text=in_pin,
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layer=self.bus_layer,
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offset=in_pos,
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height=via.mod.second_layer_height,
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width=via.mod.second_layer_width)
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def route_output_inverters(self):
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"""
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Route all conections of the inverter outputs
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"""
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for inv_num in range(self.number_of_inputs):
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out_pin = "Abar_{}".format(inv_num)
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in_pin = "in_{}".format(inv_num)
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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# add output so that it is just below the vdd or gnd rail
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@@ -250,31 +286,11 @@ class hierarchical_predecode(design.design):
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offset=rail_pos,
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directions=self.bus_directions)
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# route input
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pin = self.inv_inst[inv_num].get_pin("A")
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inv_in_pos = pin.center()
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in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
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self.add_path(self.input_layer, [in_pos, inv_in_pos])
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=inv_in_pos)
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via=self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=in_pos)
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# Create the input pin at this location on the rail
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self.add_layout_pin_rect_center(text=in_pin,
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layer=self.bus_layer,
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offset=in_pos,
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height=via.mod.second_layer_height,
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width=via.mod.second_layer_width)
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def route_input_ands(self):
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"""
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Route the different permutations of the NAND/AND decocer cells.
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"""
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||||
|
||||
# This is a hack to fix via-to-via spacing issues, but it is currently
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# causing its own DRC problems.
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# if layer_props.hierarchical_predecode.vertical_supply:
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# below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2))
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# self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2)
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def route_and_to_rails(self):
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# This 2D array defines the connection mapping
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and_input_line_combination = self.get_and_input_line_combination()
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for k in range(self.number_of_outputs):
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@@ -13,8 +13,8 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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"""
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Pre 2x4 decoder used in hierarchical_decoder.
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"""
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def __init__(self, name, height=None):
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super().__init__( name, 2, height)
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def __init__(self, name, column_decoder=False, height=None):
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super().__init__(name, 2, column_decoder, height)
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|
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self.create_netlist()
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if not OPTS.netlist_only:
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||||
|
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@@ -13,8 +13,8 @@ class hierarchical_predecode3x8(hierarchical_predecode):
|
||||
"""
|
||||
Pre 3x8 decoder used in hierarchical_decoder.
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||||
"""
|
||||
def __init__(self, name, height=None):
|
||||
super().__init__(name, 3, height)
|
||||
def __init__(self, name, column_decoder=False, height=None):
|
||||
super().__init__(name, 3, column_decoder, height)
|
||||
|
||||
self.create_netlist()
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||||
if not OPTS.netlist_only:
|
||||
|
||||
@@ -13,8 +13,8 @@ class hierarchical_predecode4x16(hierarchical_predecode):
|
||||
"""
|
||||
Pre 4x16 decoder used in hierarchical_decoder.
|
||||
"""
|
||||
def __init__(self, name, height=None):
|
||||
super().__init__(name, 4, height)
|
||||
def __init__(self, name, column_decoder=False, height=None):
|
||||
super().__init__(name, 4, column_decoder, height)
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
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||||
|
||||
@@ -10,6 +10,7 @@ from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from vector import vector
|
||||
import debug
|
||||
from tech import layer_properties as layer_props
|
||||
|
||||
|
||||
class local_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
@@ -190,6 +191,11 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
|
||||
def route(self):
|
||||
|
||||
global_wl_layer = layer_props.global_bitcell_array.wordline_layer
|
||||
global_wl_pitch = getattr(self, "{}_pitch".format(global_wl_layer))
|
||||
global_wl_pitch_factor = layer_props.global_bitcell_array.wordline_pitch_factor
|
||||
local_wl_layer = layer_props.local_bitcell_array.wordline_layer
|
||||
|
||||
# Route the global wordlines
|
||||
for port in self.all_ports:
|
||||
if port == 0:
|
||||
@@ -204,25 +210,33 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
in_pin = self.wl_insts[port].get_pin(in_pin_name)
|
||||
|
||||
y_offset = in_pin.cy()
|
||||
|
||||
if port == 0:
|
||||
y_offset -= 2 * self.m3_pitch
|
||||
y_offset -= global_wl_pitch_factor * global_wl_pitch
|
||||
else:
|
||||
y_offset += 2 * self.m3_pitch
|
||||
|
||||
self.add_layout_pin_segment_center(text=wl_name,
|
||||
layer="m3",
|
||||
start=vector(self.wl_insts[port].lx(), y_offset),
|
||||
end=vector(self.wl_insts[port].lx() + self.wl_array.width, y_offset))
|
||||
|
||||
y_offset += global_wl_pitch_factor * global_wl_pitch
|
||||
mid = vector(in_pin.cx(), y_offset)
|
||||
self.add_path("m2", [in_pin.center(), mid])
|
||||
|
||||
self.add_layout_pin_rect_center(text=wl_name,
|
||||
layer=global_wl_layer,
|
||||
offset=mid)
|
||||
|
||||
self.add_path(local_wl_layer, [in_pin.center(), mid])
|
||||
|
||||
# A short jog to the global line
|
||||
self.add_via_stack_center(from_layer=in_pin.layer,
|
||||
to_layer="m2",
|
||||
offset=in_pin.center())
|
||||
self.add_via_center(self.m2_stack,
|
||||
offset=mid)
|
||||
|
||||
to_layer=local_wl_layer,
|
||||
offset=in_pin.center(),
|
||||
min_area=True)
|
||||
self.add_path(local_wl_layer, [in_pin.center(), mid])
|
||||
self.add_via_stack_center(from_layer=local_wl_layer,
|
||||
to_layer=global_wl_layer,
|
||||
offset=mid,
|
||||
min_area=True)
|
||||
# Add the global WL pin
|
||||
self.add_layout_pin_rect_center(text=wl_name,
|
||||
layer=global_wl_layer,
|
||||
offset=mid)
|
||||
# Route the buffers
|
||||
for port in self.all_ports:
|
||||
driver_outputs = self.driver_wordline_outputs[port]
|
||||
@@ -239,7 +253,12 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
out_loc = out_pin.lc()
|
||||
mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y)
|
||||
in_loc = in_pin.rc()
|
||||
self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc])
|
||||
|
||||
self.add_path(out_pin.layer, [out_loc, mid_loc])
|
||||
self.add_via_stack_center(from_layer=out_pin.layer,
|
||||
to_layer=in_pin.layer,
|
||||
offset=mid_loc)
|
||||
self.add_path(in_pin.layer, [mid_loc, in_loc])
|
||||
|
||||
def get_main_array_top(self):
|
||||
return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_top()
|
||||
|
||||
Reference in New Issue
Block a user