mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup bitcell_base
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@ -95,7 +95,7 @@ class bitcell_base(design.design):
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labels for pex simulation.
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"""
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# If we generated the bitcell, we already know where Q and Q_bar are
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if OPTS.bitcell is not "pbitcell":
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if OPTS.bitcell != "pbitcell":
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self.storage_net_offsets = []
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for i in range(len(self.get_storage_net_names())):
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for text in self.gds.getTexts(layer["m1"]):
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@ -105,7 +105,6 @@ class bitcell_base(design.design):
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for i in range(len(self.storage_net_offsets)):
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self.storage_net_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.storage_net_offsets[i]])
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return(self.storage_net_offsets)
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def get_bitline_offset(self):
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@ -150,7 +149,7 @@ class bitcell_base(design.design):
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of the bitcell. This is useful for making sense of offsets outside
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of the bitcell.
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"""
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if OPTS.bitcell is not "pbitcell":
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if OPTS.bitcell != "pbitcell":
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normalized_storage_net_offset = self.get_storage_net_offset()
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else:
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@ -160,7 +159,7 @@ class bitcell_base(design.design):
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Q_bar_x = net_offset[1][0] - self.leftmost_xpos
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Q_bar_y = net_offset[1][1] - self.botmost_ypos
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normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]]
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normalized_storage_net_offset = [[Q_x, Q_y], [Q_bar_x, Q_bar_y]]
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return normalized_storage_net_offset
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