Rewrote pin enclosure code to better address off grid pins.

Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.

compiler/modules/bank.py

@@ -107,8 +107,7 @@ class bank(design.design):
         if self.num_banks > 1:
             self.route_bank_select()            
         
-        self.route_vdd_gnd()
-
+        self.route_supplies()
         
     def create_modules(self):
         """ Add modules. The order should not matter! """
@@ -573,7 +572,7 @@ class bank(design.design):
             self.bank_select_inst[port].place(self.bank_select_pos)
 
         
-    def route_vdd_gnd(self):
+    def route_supplies(self):
         """ Propagate all vdd/gnd pins up to this level for all modules """
         for inst in self.insts:
             self.copy_power_pins(inst,"vdd")

compiler/modules/hierarchical_predecode.py

@@ -282,15 +282,7 @@ class hierarchical_predecode(design.design):
                 # Add pins in two locations
                 for xoffset in [in_xoffset, out_xoffset]:
                     pin_pos = vector(xoffset, nand_pin.cy())
-                    self.add_via_center(layers=("metal1", "via1", "metal2"),
-                                        offset=pin_pos,
-                                        rotate=90)
-                    self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                        offset=pin_pos,
-                                        rotate=90)
-                    self.add_layout_pin_rect_center(text=n,
-                                                    layer="metal3",
-                                                    offset=pin_pos)
+                    self.add_power_pin(n, pin_pos)