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Refactored to utilize OOP

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This commit is contained in:
mrg
2020-10-13 11:07:31 -07:00
parent 68d74737f7
commit 6a1f12b62d
6 changed files with 59 additions and 37 deletions
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compiler/modules/bitcell_base_array.py
+4 -5
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@@ -48,9 +48,6 @@ class bitcell_base_array(design.design):
# Make a flat list too
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
# def get_all_wordline_names(self, prefix=""):
# return [prefix + x for x in self.all_wordline_names]
def create_all_wordline_names(self, remove_num_wordlines=0):
for row in range(self.row_size - remove_num_wordlines):
for port in self.all_ports:
@@ -67,8 +64,10 @@ class bitcell_base_array(design.design):
self.add_pin(self.supplies[1], "GROUND")
def get_bitcell_pins(self, row, col):
""" Creates a list of connections in the bitcell,
indexed by column and row, for instance use in bitcell_array """
"""
Creates a list of connections in the bitcell,
indexed by column and row, for instance use in bitcell_array
"""
bitcell_pins = []
for port in self.all_ports:
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])