mirror of https://github.com/VLSIDA/OpenRAM.git
add example of writing out simulation netlist
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@ -26,6 +26,8 @@ class rom_bank_test(openram_test):
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1)
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1)
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self.local_check(a)
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self.local_check(a)
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print('wriitng file')
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a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
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openram.end_openram()
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openram.end_openram()
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# run the test from the command line
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# run the test from the command line
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@ -33,4 +35,4 @@ if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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unittest.main(testRunner=debugTestRunner())
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