Make bitcell width/height not static. Update modules to use it for pbitcell.

compiler/modules/delay_chain.py

@@ -53,11 +53,6 @@ class delay_chain(design.design):
         self.add_pin("gnd")
 
     def add_modules(self):
-        from importlib import reload
-        c = reload(__import__(OPTS.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.bitcell = self.mod_bitcell()
-
         self.inv = pinv(route_output=False)
         self.add_mod(self.inv)
 

compiler/modules/hierarchical_decoder.py

@@ -24,7 +24,8 @@ class hierarchical_decoder(design.design):
         from importlib import reload
         c = reload(__import__(OPTS.bitcell))
         self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.bitcell_height = self.mod_bitcell.height
+        b = self.mod_bitcell()
+        self.bitcell_height = b.height
 
         self.NAND_FORMAT = "DEC_NAND[{0}]"
         self.INV_FORMAT = "DEC_INV_[{0}]"

compiler/modules/sense_amp_array.py

@@ -57,10 +57,11 @@ class sense_amp_array(design.design):
         self.amp = self.mod_sense_amp("sense_amp")
         self.add_mod(self.amp)
 
+        # This is just used for measurements,
+        # so don't add the module
         c = reload(__import__(OPTS.bitcell))
         self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
-        self.add_mod(self.bitcell)
         
     def create_sense_amp_array(self):
         self.local_insts = []

compiler/modules/wordline_driver.py

@@ -50,6 +50,13 @@ class wordline_driver(design.design):
 
 
     def add_modules(self):
+        # This is just used for measurements,
+        # so don't add the module
+        from importlib import reload
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
+        self.bitcell = self.mod_bitcell()
+
         self.inv = pinv()
         self.add_mod(self.inv)
 
@@ -59,11 +66,6 @@ class wordline_driver(design.design):
         self.nand2 = pnand2()
         self.add_mod(self.nand2)
         
-        from importlib import reload
-        c = reload(__import__(OPTS.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.bitcell = self.mod_bitcell()
-        self.add_mod(self.bitcell)
 
     def route_vdd_gnd(self):
         """ Add a pin for each row of vdd/gnd which are must-connects next level up. """

compiler/modules/write_driver_array.py

@@ -58,11 +58,12 @@ class write_driver_array(design.design):
         self.mod_write_driver = getattr(c, OPTS.write_driver)
         self.driver = self.mod_write_driver("write_driver")
         self.add_mod(self.driver)
-        
+
+        # This is just used for measurements,
+        # so don't add the module
         c = reload(__import__(OPTS.bitcell))
         self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
-        self.add_mod(self.bitcell)
 
     def create_write_array(self):
         self.driver_insts = {}