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Fix spare_wen IO pin names

This commit is contained in:
mrg 2021-06-18 10:44:35 -07:00
parent 1299989332
commit 693a81fa8d
2 changed files with 22 additions and 16 deletions
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12
compiler/sram/sram_1bank.py
View File

@ -306,11 +306,17 @@ class sram_1bank(sram_base):
start_layer=pin_layer) start_layer=pin_layer)
if port in self.write_ports: if port in self.write_ports:
for bit in range(self.num_spare_cols): if self.num_spare_cols == 1:
self.add_io_pin(self.spare_wen_dff_insts[port], self.add_io_pin(self.spare_wen_dff_insts[port],
"din_{}".format(bit), "din_{}".format(0),
"spare_wen{0}[{1}]".format(port, bit), "spare_wen{0}".format(port),
start_layer=pin_layer) start_layer=pin_layer)
else:
for bit in range(self.num_spare_cols):
self.add_io_pin(self.spare_wen_dff_insts[port],
"din_{}".format(bit),
"spare_wen{0}[{1}]".format(port, bit),
start_layer=pin_layer)
def route_layout(self): def route_layout(self):
""" Route a single bank SRAM """ """ Route a single bank SRAM """

2
compiler/sram/sram_base.py
View File

@ -709,7 +709,7 @@ class sram_base(design, verilog, lef):
outputs.append("bank_spare_wen{}".format(port)) outputs.append("bank_spare_wen{}".format(port))
else: else:
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit)) inputs.append("spare_wen{}_{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)