Verilog ROM model created for testing

compiler/modules/rom_bank.py

@@ -10,13 +10,14 @@ import datetime
 from math import ceil, log
 from openram.base import vector
 from openram.base import design
+from openram.base import rom_verilog
 from openram import OPTS, print_time
 from openram.sram_factory import factory
 from openram.tech import drc, layer, parameter
 from openram.router import router_tech
 
 
-class rom_bank(design):
+class rom_bank(design,rom_verilog):
 
     """
     Rom data bank with row and column decoder + control logic
@@ -509,4 +510,4 @@ class rom_bank(design):
         rtr=router(layers=self.m3_stack,
                    design=self,
                    bbox=bbox)
-        rtr.escape_route(pins_to_route)
+        rtr.escape_route(pins_to_route)

compiler/modules/sram_1bank.py

@@ -25,9 +25,13 @@ class sram_1bank(design, verilog, lef):
     Procedures specific to a one bank SRAM.
     """
     def __init__(self, name, sram_config):
+        print("sram_1bank debug: init")
         design.__init__(self, name)
+        print("sram_1bank debug: design init")
         lef.__init__(self, ["m1", "m2", "m3", "m4"])
+        print("sram_1bank debug: lef init")
         verilog.__init__(self)
+        print("sram_1bank debug: verilog init")
 
         self.sram_config = sram_config
         sram_config.set_local_config(self)