Added graph functions to compute analytical delay based on graph path.

compiler/pgates/pinv.py

@@ -276,7 +276,12 @@ class pinv(pgate.pgate):
         """Return the capacitance of the gate connection in generic capacitive
            units relative to the minimum width of a transistor"""
         return self.nmos_size + self.pmos_size
-        
+      
+    def input_load(self):
+        """Return the capacitance of the gate connection in generic capacitive
+           units relative to the minimum width of a transistor"""
+        return self.nmos_size + self.pmos_size
+      
     def get_stage_effort(self, cout, inp_is_rise=True):
         """Returns an object representing the parameters for delay in tau units.
            Optional is_rise refers to the input direction rise/fall. Input inverted by this stage.

compiler/pgates/pnand2.py

@@ -253,7 +253,11 @@ class pnand2(pgate.pgate):
     def get_cin(self):
         """Return the relative input capacitance of a single input"""
         return self.nmos_size+self.pmos_size
-        
+    
+    def input_load(self):
+        """Return the relative input capacitance of a single input"""
+        return self.nmos_size+self.pmos_size
+    
     def get_stage_effort(self, cout, inp_is_rise=True):
         """Returns an object representing the parameters for delay in tau units.
            Optional is_rise refers to the input direction rise/fall. Input inverted by this stage.

compiler/pgates/single_level_column_mux.py

@@ -189,7 +189,7 @@ class single_level_column_mux(pgate.pgate):
                       width=self.bitcell.width,
                       height=self.height)
         
-    def analytical_delay(self, corner, slew, load):
+    def get_stage_effort(self, corner, slew, load):
         """Returns relative delay that the column mux. Difficult to convert to LE model."""
         parasitic_delay = 1
         cin = 2*self.tx_size #This is not CMOS, so using this may be incorrect.