Added graph functions to compute analytical delay based on graph path.

compiler/bitcells/bitcell.py

@@ -36,12 +36,22 @@ class bitcell(design.design):
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
         
-    def analytical_delay(self, corner, slew, load=0, swing = 0.5):
+    def get_stage_effort(self, load):
         parasitic_delay = 1
         size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
         cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
         return logical_effort.logical_effort('bitline', size, cin, load, parasitic_delay, False)
  
+    def input_load(self):
+        """Return the relative capacitance of the access transistor gates"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
+        
+        #FIXME: The graph algorithm will apply this capacitance to the bitline load as they cannot be
+        # distinguished currently
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin
+ 
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
         row_pins = ["wl"]    

compiler/bitcells/bitcell_1rw_1r.py

@@ -141,8 +141,8 @@ class bitcell_1rw_1r(design.design):
         pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
         #Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"])   
-        graph.add_edge(pin_dict["wl0"], pin_dict["br0"])   
+        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)   
+        graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)   
         # Port 1 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"])   
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"])   
+        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)   
+        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)   

compiler/bitcells/bitcell_1w_1r.py

@@ -139,6 +139,6 @@ class bitcell_1w_1r(design.design):
         pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
         #Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"])   
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"])     
+        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)   
+        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)     
         # Port 1 is a write port, so its timing is not considered here.      

compiler/bitcells/pbitcell.py

@@ -973,6 +973,6 @@ class pbitcell(design.design):
 
         for pin_zip in [rw_pin_names, r_pin_names]: 
             for wl,bl,br in pin_zip:
-                graph.add_edge(pin_dict[wl],pin_dict[bl])
-                graph.add_edge(pin_dict[wl],pin_dict[br])
+                graph.add_edge(pin_dict[wl],pin_dict[bl], self)
+                graph.add_edge(pin_dict[wl],pin_dict[br], self)
 

compiler/bitcells/replica_bitcell_1rw_1r.py

@@ -46,8 +46,8 @@ class replica_bitcell_1rw_1r(design.design):
         pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
         #Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"])   
-        graph.add_edge(pin_dict["wl0"], pin_dict["br0"])   
+        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)   
+        graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)   
         # Port 1 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"])   
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"])  

compiler/bitcells/replica_bitcell_1w_1r.py

@@ -47,6 +47,6 @@ class replica_bitcell_1w_1r(design.design):
         pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
         #Edges hardcoded here. Essentially wl->bl/br for the read port.
         # Port 1 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"])   
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"])   
+        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)   
+        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)   
         # Port 0 is a write port, so its timing is not considered here.