Refactor bitcell to bitcell_base. Pep8 format bitcells.

compiler/bitcells/bitcell.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,parameter,drc
+from tech import GDS, layer
-import logical_effort
+import bitcell_base
 
-class bitcell(design.design):
+
+class bitcell(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so
@@ -22,12 +22,14 @@ class bitcell(design.design):
     pin_names = ["bl", "br", "wl", "vdd", "gnd"]
     storage_nets = ['Q', 'Qbar']
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
-    (width,height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"])
+    (width, height) = utils.get_libcell_size("cell_6t",
+                                             GDS["unit"],
+                                             layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "cell_6t")
+        bitcell_base.bitcell_base.__init__(self, "cell_6t")
         debug.info(2, "Create bitcell")
 
         self.width = bitcell.width
@@ -36,12 +38,6 @@ class bitcell(design.design):
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
         
-    def get_stage_effort(self, load):
-        parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        return logical_effort.logical_effort('bitline', size, cin, load, parasitic_delay, False)
- 
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
         row_pins = ["wl"]
@@ -64,43 +60,22 @@ class bitcell(design.design):
         
     def get_bl_name(self, port=0):
         """Get bl name"""
-        debug.check(port==0,"One port for bitcell only.")
+        debug.check(port == 0, "One port for bitcell only.")
         return "bl"
     
     def get_br_name(self, port=0):
         """Get bl name"""
-        debug.check(port==0,"One port for bitcell only.")
+        debug.check(port == 0, "One port for bitcell only.")
         return "br"
 
     def get_wl_name(self, port=0):
         """Get wl name"""
-        debug.check(port==0,"One port for bitcell only.")
+        debug.check(port == 0, "One port for bitcell only.")
         return "wl"
     
-    def analytical_power(self, corner, load):
-        """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
-        leakage = spice["bitcell_leakage"]
-        dynamic = 0 #temporary
-        total_power = self.return_power(dynamic, leakage)
-        return total_power
-  
-    def get_storage_net_names(self):
-        """Returns names of storage nodes in bitcell in  [non-inverting, inverting] format."""
-        #Checks that they do exist
-        if self.nets_match:
-            return self.storage_nets
-        else:
-            debug.info(1,"Storage nodes={} not found in spice file.".format(self.storage_nets))
-            return None
-    
-    def input_load(self):
-        """Return the relative capacitance of the access transistor gates"""
-        
-        # FIXME: This applies to bitline capacitances as well.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
-
     def build_graph(self, graph, inst_name, port_nets):
-        """Adds edges based on inputs/outputs. Overrides base class function."""
+        """
+        Adds edges based on inputs/outputs.
+        Overrides base class function.
+        """
         self.add_graph_edges(graph, port_nets)

compiler/bitcells/bitcell_1rw_1r.py

@@ -5,13 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,parameter,drc
+from tech import GDS, layer, parameter, drc
 import logical_effort
+import bitcell_base
 
-class bitcell_1rw_1r(design.design):
+
+class bitcell_1rw_1r(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so
@@ -20,14 +21,17 @@ class bitcell_1rw_1r(design.design):
     """
 
     pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
-    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] 
+    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", 
+                 "INPUT", "INPUT", "POWER", "GROUND"] 
     storage_nets = ['Q', 'Q_bar']
-    (width,height) = utils.get_libcell_size("cell_1rw_1r", GDS["unit"], layer["boundary"])
+    (width, height) = utils.get_libcell_size("cell_1rw_1r",
+                                             GDS["unit"],
+                                             layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "cell_1rw_1r", GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "cell_1rw_1r")
+        bitcell_base.bitcell_base.__init__(self, "cell_1rw_1r")
         debug.info(2, "Create bitcell with 1RW and 1R Port")
 
         self.width = bitcell_1rw_1r.width
@@ -36,15 +40,11 @@ class bitcell_1rw_1r(design.design):
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
         
-    def get_stage_effort(self, load):
-        parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        read_port_load = 0.5 #min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
-   
     def get_bitcell_pins(self, col, row):
-        """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
+        """ 
+        Creates a list of connections in the bitcell,
+        indexed by column and row, for instance use in bitcell_array
+        """
         bitcell_pins = ["bl0_{0}".format(col),
                         "br0_{0}".format(col),
                         "bl1_{0}".format(col),
@@ -97,49 +97,24 @@ class bitcell_1rw_1r(design.design):
     
     def get_bl_name(self, port=0):
         """Get bl name by port"""
-        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
         return "bl{}".format(port)
     
     def get_br_name(self, port=0):
         """Get bl name by port"""
-        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
         return "br{}".format(port)
 
     def get_wl_name(self, port=0):
         """Get wl name by port"""
-        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
         return "wl{}".format(port)
     
-    def analytical_power(self, corner, load):
-        """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
-        leakage = spice["bitcell_leakage"]
-        dynamic = 0 #temporary
-        total_power = self.return_power(dynamic, leakage)
-        return total_power
-
-    def input_load(self):
-        """Return the relative capacitance of the access transistor gates"""
-        
-        # FIXME: This applies to bitline capacitances as well.
-        # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
-        
-    def get_storage_net_names(self):
-        """Returns names of storage nodes in bitcell in  [non-inverting, inverting] format."""
-        #Checks that they do exist
-        if self.nets_match:
-            return self.storage_nets
-        else:
-            debug.info(1,"Storage nodes={} not found in spice file.".format(self.storage_nets))
-            return None    
-        
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
+        pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
-        #Edges hardcoded here. Essentially wl->bl/br for both ports.
+        # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
         graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
         graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)

compiler/bitcells/bitcell_1w_1r.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,parameter,drc
+from tech import GDS, layer
-import logical_effort
+import bitcell_base
 
-class bitcell_1w_1r(design.design):
+
+class bitcell_1w_1r(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so
@@ -20,14 +20,17 @@ class bitcell_1w_1r(design.design):
     """
 
     pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
-    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
+    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
+                 "INPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Q_bar']
-    (width,height) = utils.get_libcell_size("cell_1w_1r", GDS["unit"], layer["boundary"])
+    (width, height) = utils.get_libcell_size("cell_1w_1r",
+                                             GDS["unit"],
+                                             layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "cell_1w_1r")
+        bitcell_base.bitcell_base.__init__(self, "cell_1w_1r")
         debug.info(2, "Create bitcell with 1W and 1R Port")
 
         self.width = bitcell_1w_1r.width
@@ -36,15 +39,11 @@ class bitcell_1w_1r(design.design):
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
 
-    def get_stage_effort(self, load):
-        parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        read_port_load = 0.5 #min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
-   
     def get_bitcell_pins(self, col, row):
-        """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
+        """
+        Creates a list of connections in the bitcell,
+        indexed by column and row, for instance use in bitcell_array
+        """
         bitcell_pins = ["bl0_{0}".format(col),
                         "br0_{0}".format(col),
                         "bl1_{0}".format(col),
@@ -105,39 +104,14 @@ class bitcell_1w_1r(design.design):
     
     def get_wl_name(self, port=0):
         """Get wl name by port"""
-        debug.check(port<2,"Two ports for bitcell_1rw_1r only.")
+        debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
         return "wl{}".format(port)
     
-    def analytical_power(self, corner, load):
-        """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
-        leakage = spice["bitcell_leakage"]
-        dynamic = 0 #temporary
-        total_power = self.return_power(dynamic, leakage)
-        return total_power
-
-    def input_load(self):
-        """Return the relative capacitance of the access transistor gates"""
-        
-        # FIXME: This applies to bitline capacitances as well.
-        # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
-        
-    def get_storage_net_names(self):
-        """Returns names of storage nodes in bitcell in  [non-inverting, inverting] format."""
-        #Checks that they do exist
-        if self.nets_match:
-            return self.storage_nets
-        else:
-            debug.info(1,"Storage nodes={} not found in spice file.".format(self.storage_nets))
-            return None    
-        
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
+        pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
-        #Edges hardcoded here. Essentially wl->bl/br for both ports.
+        # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)

compiler/bitcells/bitcell_base.py

@@ -0,0 +1,87 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+import debug
+import design
+import logical_effort
+from tech import parameter, drc
+
+
+class bitcell_base(design.design):
+    """
+    Base bitcell parameters to be over-riden.
+    """
+    def __init__(self, name):
+        design.design.__init__(self, name)
+
+    def get_stage_effort(self, load):
+        parasitic_delay = 1
+        # This accounts for bitline being drained
+        # thought the access TX and internal node
+        size = 0.5
+        # Assumes always a minimum sizes inverter.
+        # Could be specified in the tech.py file.
+        cin = 3
+        # min size NMOS gate load
+        read_port_load = 0.5
+
+        return logical_effort.logical_effort('bitline',
+                                             size,
+                                             cin,
+                                             load + read_port_load,
+                                             parasitic_delay,
+                                             False)
+
+    def analytical_power(self, corner, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        # FIXME
+        dynamic = 0
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
+    def input_load(self):
+        """ Return the relative capacitance of the access transistor gates """
+        
+        # FIXME: This applies to bitline capacitances as well.
+        # FIXME: sizing is not accurate with the handmade cell.
+        # Change once cell widths are fixed.
+        access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
+        return 2 * access_tx_cin
+        
+    def get_wl_cin(self):
+        """Return the relative capacitance of the access transistor gates"""
+        # This is a handmade cell so the value must be entered
+        # in the tech.py file or estimated.
+        # Calculated in the tech file by summing the widths of all
+        # the related gates and dividing by the minimum width.
+        # FIXME: sizing is not accurate with the handmade cell.
+        # Change once cell widths are fixed.
+        access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
+        return 2 * access_tx_cin
+
+    def get_storage_net_names(self):
+        """
+        Returns names of storage nodes in bitcell in
+        [non-inverting, inverting] format.
+        """
+        # Checks that they do exist
+        if self.nets_match:
+            return self.storage_nets
+        else:
+            fmt_str = "Storage nodes={} not found in spice file."
+            debug.info(1, fmt_str.format(self.storage_nets))
+            return None
+    
+    def build_graph(self, graph, inst_name, port_nets):
+        """
+        By default, bitcells won't be part of the graph.
+
+        """
+        return

compiler/bitcells/dummy_bitcell.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,parameter,drc
+from tech import GDS, layer
-import logical_effort
+import bitcell_base
 
-class dummy_bitcell(design.design):
+
+class dummy_bitcell(bitcell_base.bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so
@@ -20,29 +20,18 @@ class dummy_bitcell(design.design):
     """
 
     pin_names = ["bl", "br", "wl", "vdd", "gnd"]
-    (width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"])
+    (width, height) = utils.get_libcell_size("dummy_cell_6t",
+                                             GDS["unit"],
+                                             layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "dummy_cell_6t")
+        bitcell_base.bitcell_base.__init__(self, "dummy_cell_6t")
         debug.info(2, "Create dummy bitcell")
 
         self.width = dummy_bitcell.width
         self.height = dummy_bitcell.height
         self.pin_map = dummy_bitcell.pin_map
 
-    def analytical_power(self, corner, load):
-        """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
-        leakage = spice["bitcell_leakage"]
-        dynamic = 0 #temporary
-        total_power = self.return_power(dynamic, leakage)
-        return total_power
 
-    def get_wl_cin(self):
-        """Return the relative capacitance of the access transistor gates"""
-        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
-        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin

compiler/bitcells/dummy_bitcell_1rw_1r.py

@@ -5,12 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,drc,parameter
+from tech import GDS, layer
+import bitcell_base
 
-class dummy_bitcell_1rw_1r(design.design):
+
+class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
     """
     A single bit cell which is forced to store a 0.
     This module implements the single memory cell used in the design. It
@@ -18,13 +19,18 @@ class dummy_bitcell_1rw_1r(design.design):
     the technology library. """
 
     pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
-    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]  
+    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
-    (width,height) = utils.get_libcell_size("dummy_cell_1rw_1r", GDS["unit"], layer["boundary"])
+                 "INPUT", "INPUT", "POWER", "GROUND"]
-    pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_1rw_1r", GDS["unit"])
+    (width, height) = utils.get_libcell_size("dummy_cell_1rw_1r",
+                                             GDS["unit"],
+                                             layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names,
+                                     "dummy_cell_1rw_1r",
+                                     GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "dummy_cell_1rw_1r")
+        bitcell_base.bitcell_base.__init__(self, "dummy_cell_1rw_1r")
         debug.info(2, "Create dummy bitcell 1rw+1r object")
 
         self.width = dummy_bitcell_1rw_1r.width
@@ -32,14 +38,3 @@ class dummy_bitcell_1rw_1r(design.design):
         self.pin_map = dummy_bitcell_1rw_1r.pin_map
         self.add_pin_types(self.type_list)
 
-    def get_wl_cin(self):
-        """Return the relative capacitance of the access transistor gates"""
-        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
-        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
-        #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
-
-    def build_graph(self, graph, inst_name, port_nets):        
-        """Dummy bitcells are cannot form a path and be part of the timing graph"""
-        return 

compiler/bitcells/dummy_bitcell_1w_1r.py

@@ -5,12 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import design
 import debug
 import utils
-from tech import GDS,layer,drc,parameter
+from tech import GDS, layer
+import bitcell_base
 
-class dummy_bitcell_1w_1r(design.design):
+
+class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
     """
     A single bit cell which is forced to store a 0.
     This module implements the single memory cell used in the design. It
@@ -18,13 +19,18 @@ class dummy_bitcell_1w_1r(design.design):
     the technology library. """
 
     pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
-    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] 
+    type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
-    (width,height) = utils.get_libcell_size("dummy_cell_1w_1r", GDS["unit"], layer["boundary"])
+                 "INPUT", "INPUT", "POWER", "GROUND"]
-    pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_1w_1r", GDS["unit"])
+    (width, height) = utils.get_libcell_size("dummy_cell_1w_1r",
+                                             GDS["unit"],
+                                             layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names,
+                                     "dummy_cell_1w_1r",
+                                     GDS["unit"])
 
     def __init__(self, name=""):
         # Ignore the name argument
-        design.design.__init__(self, "dummy_cell_1w_1r")
+        bitcell_base.bitcell_base.__init__(self, "dummy_cell_1w_1r")
         debug.info(2, "Create dummy bitcell 1w+1r object")
 
         self.width = dummy_bitcell_1w_1r.width
@@ -32,14 +38,4 @@ class dummy_bitcell_1w_1r(design.design):
         self.pin_map = dummy_bitcell_1w_1r.pin_map
         self.add_pin_types(self.type_list)
 
-    def get_wl_cin(self):
-        """Return the relative capacitance of the access transistor gates"""
-        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
-        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
-        #FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
 
-    def build_graph(self, graph, inst_name, port_nets):        
-        """Dummy bitcells are cannot form a path and be part of the timing graph"""
-        return