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Fix error in no spare column verilog

This commit is contained in:
mrg 2021-06-18 08:41:26 -07:00
parent 81d20ec2aa
commit 67877175b2
3 changed files with 12 additions and 10 deletions
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12
compiler/base/verilog.py
View File

@ -56,14 +56,14 @@ class verilog:
if self.write_size: if self.write_size:
self.vf.write("wmask{},".format(port)) self.vf.write("wmask{},".format(port))
if self.num_spare_cols > 0: if self.num_spare_cols > 0:
self.vf.write(" spare_wen{0},".format(port)) self.vf.write("spare_wen{0},".format(port))
self.vf.write("addr{0},din{0},dout{0}".format(port)) self.vf.write("addr{0},din{0},dout{0}".format(port))
elif port in self.write_ports: elif port in self.write_ports:
self.vf.write(" clk{0},csb{0},".format(port)) self.vf.write(" clk{0},csb{0},".format(port))
if self.write_size: if self.write_size:
self.vf.write("wmask{},".format(port)) self.vf.write("wmask{},".format(port))
if self.num_spare_cols > 0: if self.num_spare_cols > 0:
self.vf.write(" spare_wen{0},".format(port)) self.vf.write("spare_wen{0},".format(port))
self.vf.write("addr{0},din{0}".format(port)) self.vf.write("addr{0},din{0}".format(port))
elif port in self.read_ports: elif port in self.read_ports:
self.vf.write(" clk{0},csb{0},addr{0},dout{0}".format(port)) self.vf.write(" clk{0},csb{0},addr{0},dout{0}".format(port))
@ -192,10 +192,10 @@ class verilog:
self.vf.write(" input web{0}; // active low write control\n".format(port)) self.vf.write(" input web{0}; // active low write control\n".format(port))
if self.write_size: if self.write_size:
self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port)) self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port))
if self.num_spare_cols > 1: if self.num_spare_cols == 1:
self.vf.write(" input [{1}:0] spare_wen{0}; // write mask\n".format(port, self.num_spare_cols-1)) self.vf.write(" input spare_wen{0}; // spare mask\n".format(port))
else: elif self.num_spare_cols > 1:
self.vf.write(" input spare_wen{0}; // write mask\n".format(port)) self.vf.write(" input [{1}:0] spare_wen{0}; // spare mask\n".format(port, self.num_spare_cols-1))
self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port)) self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port))
if port in self.write_ports: if port in self.write_ports:

5
compiler/tests/golden/sram_2_16_1_freepdk45.v
View File

@ -56,8 +56,9 @@ reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Write Operation : When web0 = 0, csb0 = 0 // Write Operation : When web0 = 0, csb0 = 0
always @ (negedge clk0) always @ (negedge clk0)
begin : MEM_WRITE0 begin : MEM_WRITE0
if ( !csb0_reg && !web0_reg ) if ( !csb0_reg && !web0_reg ) begin
mem[addr0_reg] = din0_reg; mem[addr0_reg][1:0] = din0_reg[1:0];
end
end end
// Memory Read Block Port 0 // Memory Read Block Port 0

5
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
View File

@ -56,8 +56,9 @@ reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Write Operation : When web0 = 0, csb0 = 0 // Write Operation : When web0 = 0, csb0 = 0
always @ (negedge clk0) always @ (negedge clk0)
begin : MEM_WRITE0 begin : MEM_WRITE0
if ( !csb0_reg && !web0_reg ) if ( !csb0_reg && !web0_reg ) begin
mem[addr0_reg] = din0_reg; mem[addr0_reg][1:0] = din0_reg[1:0];
end
end end
// Memory Read Block Port 0 // Memory Read Block Port 0