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Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.

This commit is contained in:
mrg 2022-07-20 10:27:30 -07:00
parent 5ad97aa636
commit 6707a93c3c
1 changed files with 2 additions and 13 deletions
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15
compiler/modules/replica_bitcell_array.py
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@ -309,8 +309,8 @@ class replica_bitcell_array(bitcell_base_array):
# This creates space for the unused wordline connections as well as the # This creates space for the unused wordline connections as well as the
# row-based or column based power and ground lines. # row-based or column based power and ground lines.
self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0])) self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2])) self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
self.unused_offset = vector(0.25, 0.25) self.unused_offset = vector(0.25, 0.25)
# This is a bitcell x bitcell offset to scale # This is a bitcell x bitcell offset to scale
@ -495,16 +495,7 @@ class replica_bitcell_array(bitcell_base_array):
else: else:
bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports)) bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
wl_layer = bitcell.wl_layer
wl_dir = bitcell.wl_dir
bl_layer = bitcell.bl_layer
bl_dir = bitcell.bl_dir
vdd_layer = bitcell.vdd_layer
vdd_dir = bitcell.vdd_dir vdd_dir = bitcell.vdd_dir
gnd_layer = bitcell.gnd_layer
gnd_dir = bitcell.gnd_dir gnd_dir = bitcell.gnd_dir
# vdd/gnd are only connected in the perimeter cells # vdd/gnd are only connected in the perimeter cells
@ -514,8 +505,6 @@ class replica_bitcell_array(bitcell_base_array):
top_bot_mult = 1 top_bot_mult = 1
left_right_mult = 1 left_right_mult = 1
vdd_locs = []
gnd_locs = []
# There are always vertical pins for the WLs on the left/right if we have unused wordlines # There are always vertical pins for the WLs on the left/right if we have unused wordlines
self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult) self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult) self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)