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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Use channel for dffs all at once
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@@ -108,8 +108,21 @@ class write_mask_and_array(design.design):
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end=vector(self.width, en_pin.cy()))
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for i in range(self.num_wmasks):
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# Route the A pin over to the left so that it doesn't conflict with the sense
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# amp output which is usually in the center
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a_pin = self.and2_insts[i].get_pin("A")
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a_pos = a_pin.center()
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in_pos = vector(self.and2_insts[i].lx(),
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a_pos.y)
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self.add_via_stack_center(from_layer=a_pin.layer,
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to_layer="m2",
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offset=in_pos)
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self.add_layout_pin_rect_center(text="wmask_in_{0}".format(i),
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layer="m2",
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offset=in_pos)
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self.add_path(a_pin.layer, [in_pos, a_pos])
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# Copy remaining layout pins
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self.copy_layout_pin(self.and2_insts[i], "A", "wmask_in_{0}".format(i))
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self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i))
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# Add via connections to metal3 for AND array's B pin
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@@ -122,7 +135,7 @@ class write_mask_and_array(design.design):
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for supply in ["gnd", "vdd"]:
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supply_pin=self.and2_insts[i].get_pin(supply)
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if "li" in layer:
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self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions = ("H", "H"))
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self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions=("H", "H"))
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else:
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self.add_power_pin(supply, supply_pin.center())
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