mirror of https://github.com/VLSIDA/OpenRAM.git
Use default bitcell name if one isn't provided.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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@ -36,6 +36,9 @@ class bitcell(bitcell_base.bitcell_base):
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storage_nets = ['Q', 'Q_bar']
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, name=""):
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def __init__(self, name=""):
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if not name:
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name = self.name
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bitcell_base.bitcell_base.__init__(self, name)
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bitcell_base.bitcell_base.__init__(self, name)
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debug.info(2, "Create bitcell")
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debug.info(2, "Create bitcell")
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