mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 Formatting
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@ -5,12 +5,10 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys
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import datetime
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import getpass
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import debug
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from globals import OPTS, print_time
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from sram_config import sram_config
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class sram():
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"""
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@ -50,7 +48,6 @@ class sram():
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if not OPTS.is_unit_test:
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print_time("SRAM creation", datetime.datetime.now(), start_time)
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def sp_write(self, name):
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self.s.sp_write(name)
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@ -63,7 +60,6 @@ class sram():
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def verilog_write(self, name):
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self.s.verilog_write(name)
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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@ -108,7 +104,6 @@ class sram():
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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start_time = datetime.datetime.now()
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from shutil import copyfile
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