mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
Rework replica_bitcell_array supplies
Uses layer and direction preferences in tech file. Places straps on left/right or top/bottom.
This commit is contained in:
mrg
@@ -99,4 +99,4 @@ class col_cap_array(bitcell_base_array):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.copy_power_pin(pin)
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self.copy_layout_pin(inst, pin_name)
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@@ -145,6 +145,15 @@ class dff_buf_array(design.design):
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return dout_bar_name
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def route_supplies(self):
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for row in range(self.rows):
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vdd0_pin=self.dff_insts[row, 0].get_pin("vdd")
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vddn_pin=self.dff_insts[row, self.columns - 1].get_pin("vdd")
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self.add_path(vdd0_pin.layer, [vdd0_pin.lc(), vddn_pin.rc()], width=vdd0_pin.height())
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gnd0_pin=self.dff_insts[row, 0].get_pin("gnd")
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gndn_pin=self.dff_insts[row, self.columns - 1].get_pin("gnd")
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self.add_path(gnd0_pin.layer, [gnd0_pin.lc(), gndn_pin.rc()], width=gnd0_pin.height())
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if OPTS.experimental_power and self.rows > 1:
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# Vertical straps on ends if multiple rows
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left_dff_insts = [self.dff_insts[x, 0] for x in range(self.rows)]
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@@ -6,7 +6,8 @@
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import debug
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from bitcell_base_array import bitcell_base_array
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from tech import drc, spice, cell_properties
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from tech import drc, spice, preferred_directions
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from tech import cell_properties as props
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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@@ -309,7 +310,7 @@ class replica_bitcell_array(bitcell_base_array):
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# row-based or column based power and ground lines.
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self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2]))
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self.unused_offset = vector(2 * self.horizontal_pitch, 2 * self.vertical_pitch)
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self.unused_offset = vector(0.25, 0.25)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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@@ -461,38 +462,67 @@ class replica_bitcell_array(bitcell_base_array):
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def route_supplies(self):
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bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
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wl_layer = bitcell.wl_layer
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wl_dir = bitcell.wl_dir
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bl_layer = bitcell.bl_layer
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bl_dir = bitcell.bl_dir
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vdd_layer = bitcell.vdd_layer
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vdd_dir = bitcell.vdd_dir
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gnd_layer = bitcell.gnd_layer
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gnd_dir = bitcell.gnd_dir
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# vdd/gnd are only connected in the perimeter cells
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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vdd_leftx = 0
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vdd_rightx = 0
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gnd_leftx = 0
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gnd_rightx = 0
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# For the wordlines
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top_bot_mult = 1
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left_right_mult = 1
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vdd_locs = []
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gnd_locs = []
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# There are always vertical pins for the WLs on the left/right if we have unused wordlines
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self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
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self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
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left_right_mult = 3
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if gnd_dir == "V":
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self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
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self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
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top_bot_mult = 3
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if vdd_dir == "V":
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self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)
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self.bot_vdd_locs = self.route_side_pin("vdd", "bot", top_bot_mult)
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elif vdd_dir == "H":
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self.left_vdd_locs = self.route_side_pin("vdd", "left", left_right_mult)
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self.right_vdd_locs = self.route_side_pin("vdd", "right", left_right_mult)
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else:
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debug.error("Invalid vdd direction {}".format(vdd_dir), -1)
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for inst in supply_insts:
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for pin in inst.get_pins("vdd"):
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(vdd_leftx, vdd_rightx) = self.connect_pin(pin, 2.5)
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if vdd_dir == "V":
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self.connect_side_pin(pin, "top", self.top_vdd_locs[0].y)
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self.connect_side_pin(pin, "bot", self.bot_vdd_locs[0].y)
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elif vdd_dir == "H":
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self.connect_side_pin(pin, "left", self.left_vdd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_vdd_locs[0].x)
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for inst in supply_insts:
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for pin in inst.get_pins("gnd"):
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(gnd_leftx, gnd_rightx) = self.connect_pin(pin)
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self.add_layout_end_pin_segment_center(text="vdd",
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layer=self.supply_stack[2],
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start=vector(vdd_leftx, 0),
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end=vector(vdd_leftx, self.height))
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self.add_layout_end_pin_segment_center(text="vdd",
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layer=self.supply_stack[2],
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start=vector(vdd_rightx, 0),
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end=vector(vdd_rightx, self.height))
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self.add_layout_end_pin_segment_center(text="gnd",
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layer=self.supply_stack[2],
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start=vector(gnd_leftx, 0),
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end=vector(gnd_leftx, self.height))
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self.add_layout_end_pin_segment_center(text="gnd",
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layer=self.supply_stack[2],
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start=vector(gnd_rightx, 0),
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end=vector(gnd_rightx, self.height))
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if gnd_dir == "V":
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self.connect_side_pin(pin, "top", self.top_gnd_locs[0].y)
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self.connect_side_pin(pin, "bot", self.bot_gnd_locs[0].y)
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elif gnd_dir == "H":
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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def route_unused_wordlines(self):
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@@ -501,41 +531,120 @@ class replica_bitcell_array(bitcell_base_array):
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap_top.get_wordline_names():
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pin = inst.get_pin(wl_name)
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self.connect_pin(pin)
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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pin = inst.get_pin(pin_name)
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self.connect_pin(pin)
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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def route_side_pin(self, name, side, offset_multiple=1):
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"""
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Routes a vertical or horizontal pin on the side of the bbox.
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The multiple specifies how many track offsets to be away from the side assuming
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(0,0) (self.width, self.height)
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"""
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if side in ["left", "right"]:
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return self.route_vertical_side_pin(name, side, offset_multiple)
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elif side in ["top", "bottom", "bot"]:
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return self.route_horizontal_side_pin(name, side, offset_multiple)
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else:
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debug.error("Invalid side {}".format(side), -1)
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def connect_pin(self, pin, offset_multiple=1):
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def route_vertical_side_pin(self, name, side, offset_multiple=1):
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"""
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Routes a vertical pin on the side of the bbox.
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"""
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if side == "left":
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bot_loc = vector(-offset_multiple * self.vertical_pitch, 0)
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top_loc = vector(-offset_multiple * self.vertical_pitch, self.height)
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elif side == "right":
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bot_loc = vector(self.width + offset_multiple * self.vertical_pitch, 0)
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top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
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pin_layer = pin.layer
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layer = self.supply_stack[2]
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self.add_path(layer, [bot_loc, top_loc])
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left_pin_loc = vector(self.dummy_col_insts[0].lx(), pin.cy())
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right_pin_loc = vector(self.dummy_col_insts[1].rx(), pin.cy())
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self.add_layout_pin_rect_center(text=name,
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layer=layer,
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offset=top_loc)
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self.add_layout_pin_rect_center(text=name,
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layer=layer,
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offset=bot_loc)
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return (bot_loc, top_loc)
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def route_horizontal_side_pin(self, name, side, offset_multiple=1):
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"""
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Routes a horizontal pin on the side of the bbox.
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"""
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if side in ["bottom", "bot"]:
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left_loc = vector(0, -offset_multiple * self.horizontal_pitch)
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right_loc = vector(self.width, -offset_multiple * self.horizontal_pitch)
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elif side == "top":
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left_loc = vector(0, self.height + offset_multiple * self.horizontal_pitch)
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right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
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layer = self.supply_stack[0]
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self.add_path(layer, [left_loc, right_loc])
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self.add_layout_pin_rect_center(text=name,
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layer=layer,
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offset=left_loc)
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self.add_layout_pin_rect_center(text=name,
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layer=layer,
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offset=right_loc)
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return (left_loc, right_loc)
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def connect_side_pin(self, pin, side, offset):
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"""
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Used to connect horizontal layers of pins to the left/right straps
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locs provides the offsets of the pin strip end points.
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"""
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if side in ["left", "right"]:
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self.connect_vertical_side_pin(pin, side, offset)
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elif side in ["top", "bottom", "bot"]:
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self.connect_horizontal_side_pin(pin, side, offset)
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else:
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debug.error("Invalid side {}".format(side), -1)
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def connect_horizontal_side_pin(self, pin, side, yoffset):
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"""
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Used to connect vertical layers of pins to the top/bottom horizontal straps
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"""
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cell_loc = pin.center()
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pin_loc = vector(cell_loc.x, yoffset)
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# Place the pins a track outside of the array
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left_loc = left_pin_loc - vector(offset_multiple * self.horizontal_pitch, 0)
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right_loc = right_pin_loc + vector(offset_multiple * self.horizontal_pitch, 0)
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self.add_via_stack_center(offset=left_loc,
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from_layer=pin_layer,
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to_layer=self.supply_stack[2],
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directions=("H", "H"))
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self.add_via_stack_center(offset=right_loc,
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from_layer=pin_layer,
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self.add_via_stack_center(offset=pin_loc,
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from_layer=pin.layer,
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to_layer=self.supply_stack[0],
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directions=("V", "V"))
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# Add a path to connect to the array
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self.add_path(pin.layer, [cell_loc, pin_loc])
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def connect_vertical_side_pin(self, pin, side, xoffset):
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"""
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Used to connect vertical layers of pins to the top/bottom vertical straps
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"""
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cell_loc = pin.center()
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pin_loc = vector(xoffset, cell_loc.y)
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# Place the pins a track outside of the array
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self.add_via_stack_center(offset=pin_loc,
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from_layer=pin.layer,
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to_layer=self.supply_stack[2],
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directions=("H", "H"))
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# Add a path to connect to the array
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self.add_path(pin_layer, [left_loc, right_loc])
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return (left_loc.x, right_loc.x)
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self.add_path(pin.layer, [cell_loc, pin_loc])
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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@@ -106,10 +106,13 @@ class row_cap_array(bitcell_base_array):
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width=self.width,
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height=wl_pin.height())
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# Add vdd/gnd via stacks
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for row in range(1, self.row_size - 1):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.copy_power_pin(pin)
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll(),
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width=pin.width(),
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height=pin.height())
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