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sky130 singlebank drc clean

This commit is contained in:
Jesse Cirimelli-Low 2021-05-03 12:52:07 -07:00
parent 3a3da9e0d7
commit 64b1946d6e
2 changed files with 29 additions and 24 deletions
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11
compiler/pgates/column_mux.py
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@ -223,10 +223,15 @@ class column_mux(pgate.pgate):
Add a well and implant over the whole cell. Also, add the Add a well and implant over the whole cell. Also, add the
pwell contact (if it exists) pwell contact (if it exists)
""" """
if(cell_props.use_strap == True and OPTS.num_ports == 1):
strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
rbc_width = self.bitcell.width + strap.width
else:
rbc_width = cell.width
# Add it to the right, aligned in between the two tx # Add it to the right, aligned in between the two tx
active_pos = vector(self.bitcell.width, active_pos = vector(rbc_width,
self.nmos_upper.by() - 0.5 * self.poly_space) self.nmos_upper.by() - 0.5 * self.poly_space)
self.add_via_center(layers=self.active_stack, self.add_via_center(layers=self.active_stack,
offset=active_pos, offset=active_pos,
implant_type="p", implant_type="p",
@ -245,5 +250,5 @@ class column_mux(pgate.pgate):
if "pwell" in layer: if "pwell" in layer:
self.add_rect(layer="pwell", self.add_rect(layer="pwell",
offset=vector(0, 0), offset=vector(0, 0),
width=self.bitcell.width, width=rbc_width,
height=self.height) height=self.height)

42
compiler/tests/19_single_bank_test.py
View File

@ -26,20 +26,20 @@ class single_bank_test(openram_test):
c = sram_config(word_size=4, c = sram_config(word_size=4,
num_words=16) num_words=16)
c.words_per_row=1 # c.words_per_row=1
factory.reset() # factory.reset()
c.recompute_sizes() # c.recompute_sizes()
debug.info(1, "No column mux") # debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c) # a = factory.create("bank", sram_config=c)
self.local_check(a) # self.local_check(a)
c.num_words=32 # c.num_words=32
c.words_per_row=2 # c.words_per_row=2
factory.reset() # factory.reset()
c.recompute_sizes() # c.recompute_sizes()
debug.info(1, "Two way column mux") # debug.info(1, "Two way column mux")
a = factory.create("bank", sram_config=c) # a = factory.create("bank", sram_config=c)
self.local_check(a) # self.local_check(a)
c.num_words=64 c.num_words=64
c.words_per_row=4 c.words_per_row=4
@ -49,14 +49,14 @@ class single_bank_test(openram_test):
a = factory.create("bank", sram_config=c) a = factory.create("bank", sram_config=c)
self.local_check(a) self.local_check(a)
c.word_size=2 #c.word_size=2
c.num_words=128 #c.num_words=128
c.words_per_row=8 #c.words_per_row=8
factory.reset() #factory.reset()
c.recompute_sizes() #c.recompute_sizes()
debug.info(1, "Eight way column mux") #debug.info(1, "Eight way column mux")
a = factory.create("bank", sram_config=c) #a = factory.create("bank", sram_config=c)
self.local_check(a) #self.local_check(a)
globals.end_openram() globals.end_openram()