mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
Decoder array and start of rom bank
This commit is contained in:
Jacob Walker
+187
-123
@@ -12,25 +12,27 @@ from .bitcell_base_array import bitcell_base_array
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from base import vector
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from globals import OPTS
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from sram_factory import factory
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import tech
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from tech import drc
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class rom_base_array(bitcell_base_array):
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def __init__(self, rows, cols, strap_spacing, bitmap, name="", column_offset=0):
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def __init__(self, rows, cols, strap_spacing, bitmap, name="", column_offset=0, route_layer="li", output_layer="m2"):
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super().__init__(name=name, rows=rows, cols=cols, column_offset=column_offset)
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#TODO: data is input in col-major order for ease of parsing, create a function to convert a row-major input to col-major
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self.data = bitmap
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self.route_layer = 'm1'
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self.strap_spacing = strap_spacing
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self.data_col_size = self.column_size
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self.array_col_size = self.column_size + math.ceil(self.column_size / strap_spacing)
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self.data = bitmap
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self.route_layer = route_layer
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self.output_layer = output_layer
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self.strap_spacing = strap_spacing
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self.data_col_size = self.column_size
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if strap_spacing != 0:
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self.array_col_size = self.column_size + math.ceil(self.column_size / strap_spacing)
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else:
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self.array_col_size = self.column_size
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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self.create_layout()
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@@ -38,31 +40,44 @@ class rom_base_array(bitcell_base_array):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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self.create_cell_instances()
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self.create_precharge_inst()
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def create_layout(self):
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self.place_array()
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self.place_wordline_contacts()
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self.place_bitline_contacts()
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self.place_precharge()
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self.place_rails()
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#self.route_bitlines()
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#self.route_wordlines()
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self.route_precharge()
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self.add_boundary()
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self.add_label("ARRAY ZERO", self.route_layer)
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self.add_label("array height", self.route_layer, [0, self.height])
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#def add_pins(self):
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def add_boundary(self):
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self.width = self.dummy.width * self.column_size
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self.height = self.dummy.height * self.row_size
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super().add_boundary()
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def add_modules(self):
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# dummy cell, # "dummy" cells represent 0
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self.dummy = factory.create(module_type="rom_dummy_cell", route_layer=self.route_layer)
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ll = self.find_lowest_coords()
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bottom_offset = - self.dummy.nmos.end_to_contact + self.precharge_inst.offset.y
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m1_offset = self.m1_width
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self.translate_all(vector(0, ll.y + 0.5 * m1_offset))
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ur = self.find_highest_coords()
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ur = vector(ur.x, ur.y - self.m1_width)
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#super().add_boundary(ll=vector(lowerx, lowery), ur=vector(upperx, uppery))
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super().add_boundary(vector(0, 0), ur)
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self.width = ur.x
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self.height = ur.y
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def add_modules(self):
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# dummy cell, "dummy" cells represent 0
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self.dummy = factory.create(module_type="rom_dummy_cell", route_layer=self.route_layer)
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#base cell with no contacts
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self.cell_nc = factory.create(module_name="base_mod_0_contact", module_type="rom_base_cell")
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@@ -77,14 +92,24 @@ class rom_base_array(bitcell_base_array):
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self.zero_tap = factory.create(module_type="rom_poly_tap", strap_length=0)
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self.gnd_rail = factory.create(module_type="rom_array_gnd_tap", length=self.row_size)
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def create_instances(self):
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self.precharge_array = factory.create(module_type="rom_precharge_array", cols=self.column_size, strap_spacing=self.strap_spacing, route_layer=self.route_layer)
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("precharge_gate", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_cell_instances(self):
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self.tap_inst = {}
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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#list of current bitline interconnect nets, starts as the same as the bitline list and is updated when new insts of cells are added
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int_bl_list = self.bitline_names[0]
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#When rotated correctly rows are word lines
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@@ -93,62 +118,61 @@ class rom_base_array(bitcell_base_array):
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# for each new strap placed, offset the column index refrenced to get correct bit in the data array
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strap_offset = 0
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#when rotated correctly cols are bit lines
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for col in range(self.array_col_size):
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# when rotated correctly cols are bit lines
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for col in range(self.column_size):
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name = "bit_r{0}_c{1}".format(row, col)
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data_col = col - strap_offset
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if col % self.strap_spacing == 0:
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name = "tap_r{0}_c{1}".format(row, col)
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print("tap instance added at c{0}, r{1}".format(col, row))
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.poly_tap)
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#print("tap instance added at c{0}, r{1}".format(col, row))
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self.tap_inst[row, col]=self.add_inst(name=name, mod=self.poly_tap)
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self.connect_inst([])
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strap_offset += 1
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continue
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name = "bit_r{0}_c{1}".format(row, col)
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if self.data[row][data_col] == 1:
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if self.data[row][col] == 1:
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# if dummy/0 cell above and below a 1, add a tx with contacts on both drain and source
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# if the first row and a 0 above, add both contacts
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# if the last row and 0 below add both contacts
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#(row == 0 and self.data[row + 1][col] == 0):
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if (row < self.row_size - 1 and row > 0 and self.data[row + 1][data_col] == 0 and self.data[row - 1][data_col] == 0) or \
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(row == self.row_size - 1 and self.data[row - 1][data_col] == 0):
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if (row < self.row_size - 1 and row > 0 and self.data[row + 1][col] == 0 and self.data[row - 1][col] == 0) or \
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(row == self.row_size - 1 and self.data[row - 1][col] == 0) or \
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(row == 0 and self.data[row + 1][col] == 0):
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new_inst = self.add_inst(name=name, mod=self.cell_ac)
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_ac)
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# if dummy/0 is below and not above, add a source contact
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# if in the first row, add a source contact
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elif (row > 0 and self.data[row - 1][data_col] == 0):
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_sc)
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elif (row > 0 and self.data[row - 1][col] == 0) or \
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(row == 0):
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elif (row < self.row_size - 1 and self.data[row + 1][data_col] == 0) or \
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new_inst=self.add_inst(name=name, mod=self.cell_sc)
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elif (row < self.row_size - 1 and self.data[row + 1][col] == 0) or \
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(row == self.row_size - 1):
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_dc)
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new_inst=self.add_inst(name=name, mod=self.cell_dc)
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else:
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self.cell_inst[row, col]=self.add_inst(name=name, mod=self.cell_nc)
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new_inst=self.add_inst(name=name, mod=self.cell_nc)
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if row == self.row_size - 1 or self.get_next_cell_in_bl(row, data_col) == -1:
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if row == self.row_size - 1 or self.get_next_cell_in_bl(row, col) == -1:
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bl_l = int_bl_list[data_col]
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bl_l = int_bl_list[col]
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bl_h = "gnd"
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else:
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bl_l = int_bl_list[data_col]
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int_bl_list[data_col] = "bl_int_{0}_{1}".format(row, data_col)
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bl_h = int_bl_list[data_col]
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bl_l = int_bl_list[col]
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int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
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bl_h = int_bl_list[col]
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self.cell_inst[row, col] = new_inst
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self.connect_inst([bl_h, bl_l, self.wordline_names[0][row], "gnd"])
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else:
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.dummy)
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new_inst = self.add_inst(name=name, mod=self.dummy)
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self.cell_inst[row, col] = new_inst
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self.connect_inst([])
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# when col = 0 bl_h is connected to vdd, otherwise connect to previous bl connection
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@@ -156,18 +180,30 @@ class rom_base_array(bitcell_base_array):
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#
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row_list.append(self.cell_inst[row, col])
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row_list.append(new_inst)
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name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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#print(*row_list)
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self.cell_inst[row, self.array_col_size]=self.add_inst(name=name, mod=self.zero_tap)
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self.tap_inst[row, self.column_size]=self.add_inst(name=name, mod=self.zero_tap)
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self.connect_inst([])
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self.cell_list.append(row_list)
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def create_precharge_inst(self):
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prechrg_pins = []
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for bl in range(self.column_size):
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prechrg_pins.append(self.bitline_names[0][bl])
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prechrg_pins.append("precharge_gate")
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prechrg_pins.append("vdd")
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self.precharge_inst = self.add_inst(name="decode_array_precharge", mod=self.precharge_array)
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self.connect_inst(prechrg_pins)
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def create_all_bitline_names(self):
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for col in range(self.column_size):
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@@ -176,110 +212,138 @@ class rom_base_array(bitcell_base_array):
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_taps(self):
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self.tap_pos = {}
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for row in range(self.row_size):
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for col in range(0, self.column_size, self.strap_spacing):
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tap_x = self.dummy.width * col
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tap_y = self.dummy.height * row
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self.tap_pos[row, col] = vector(tap_x, tap_y)
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self.tap_inst[row, col].place(self.tap_pos[row, col])
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tap_x = self.dummy.width * self.column_size + self.poly_tap.width
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tap_y = self.dummy.height * row
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self.tap_pos[row, self.column_size] = vector(tap_x, tap_y)
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self.tap_inst[row, self.column_size].place(self.tap_pos[row, self.column_size])
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def place_rails(self):
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width = drc("minwidth_" + self.route_layer)
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drc_rule = "{0}_to_{0}".format(self.route_layer)
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spacing = drc(drc_rule)
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rail_y = self.dummy.height * (self.row_size) + self.mcon_width * 0.5
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start_x = self.cell_inst[self.row_size - 1, 0].rx()
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end_x = self.cell_inst[self.row_size - 1, self.array_col_size - 1].cx()
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rail_y = self.cell_list[self.row_size - 1][0].offset.y + self.dummy.base_width + spacing
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# self.dummy.height * (self.row_size)
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start_x = self.get_pin(self.bitline_names[0][0]).cx()
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# self.cell_list[self.row_size - 1][0].offset.x
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end_x = self.get_pin(self.bitline_names[0][self.column_size - 1]).cx()
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# self.cell_list[self.row_size - 1][self.column_size - 1].offset.x
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#self.dummy.height * self.row_size
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#self.cell_inst[self.row_size - 1,0].uy()
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rail_start = vector(start_x , rail_y)
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rail_end = vector(end_x, rail_y)
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self.add_layout_pin_rect_ends( name="gnd",
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self.gnd = self.add_layout_pin_rect_ends( name="gnd",
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layer="m1",
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start=rail_start,
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end=rail_end)
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for bl in range(self.column_size):
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drain_pin = self.cell_list[self.row_size - 1][bl].get_pin("D")
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via_pos = vector(drain_pin.cx(), rail_y)
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self.add_segment_center(self.route_layer, drain_pin.center(), via_pos)
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self.add_via_stack_center(via_pos, self.route_layer, "m1", ["H", "V"])
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prechrg_vdd = self.precharge_inst.get_pin("vdd")
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def place_array(self):
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self.cell_pos = {}
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self.strap_pos = {}
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# rows are wordlines
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for row in range(self.row_size):
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strap_cols = -1
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# strap_cols = -1
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cell_y = row * (self.dummy.height)
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# columns are bit lines
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for col in range(self.array_col_size):
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cell_x = 0
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for col in range(self.column_size):
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if col % self.strap_spacing == 0:
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strap_cols += 1
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rot = 0
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else:
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rot = 90
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bit_cols = col - strap_cols
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if col == 0:
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cell_x = 0
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else:
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cell_x = (self.dummy.width * bit_cols) + (self.poly_tap.width * strap_cols)
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self.strap_pos[row, col] = vector(cell_x, cell_y)
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self.tap_inst[row, col].place(self.strap_pos[row, col])
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cell_x += self.poly_tap.width
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col], rotate=rot)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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cell_x += self.dummy.width
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self.add_label("debug", "li", self.cell_pos[row, col])
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strap_cols += 1
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bit_cols = self.array_col_size - strap_cols
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cell_x = (self.dummy.width * bit_cols) + (self.poly_tap.width * strap_cols)
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self.cell_pos[row, self.array_col_size] = vector(cell_x, cell_y)
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self.cell_inst[row, self.array_col_size].place(self.cell_pos[row, self.array_col_size])
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self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
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self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
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# tap_pin = self.cell_inst[row, self.array_col_size].get_pin("poly_tap").center()
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# self.add_layout_pin_rect_center("wl{}".format(row), "m2", tap_pin)
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def place_precharge(self):
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.dummy.nmos.end_to_contact - 2 * drc["nwell_enclose_active"])
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self.precharge_inst.place(offset=self.precharge_offset)
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self.copy_layout_pin(self.precharge_inst, "vdd")
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def place_wordline_contacts(self):
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width = drc["minwidth_{}".format(self.route_layer)]
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height = drc["minwidth_{}".format(self.route_layer)]
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offset = vector(self.poly_contact.width * 0.5, self.dummy.poly.offset.y)
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for wl in range(self.row_size):
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poly_via = self.tap_inst[wl, 0].get_pin("via")
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self.copy_layout_pin(self.tap_inst[wl, 0], "via", self.wordline_names[0][wl])
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self.add_via_stack_center(poly_via.center(), "m1", self.output_layer)
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corrected_offset = offset - vector(0.5 * width, 0.5 * height)
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# self.create_horizontal_pin_bus(self.route_layer, offset=corrected_offset, names=self.wordline_names[0], pitch=self.dummy.height, length=None)
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def place_bitline_contacts(self):
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src_pin = self.cell_nc.source_pos
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for bl in range(self.column_size):
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def route_bitlines(self):
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# self.copy_layout_pin(self.cell_list[0][bl], "S", self.bitline_names[0][bl])
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#get first nmos in col
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src_pin = self.cell_list[0][bl].get_pin("S")
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prechg_pin_name = "pre_bl{0}_out".format(bl)
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pre_pin = self.precharge_inst.get_pin(prechg_pin_name)
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#connect to main bitline wire
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# offset = src_pin_offset + vector(src_pin.x, 0)
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#get next nmos in col
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middle_offset = (pre_pin.cy() - src_pin.cy()) * 0.5
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#route source to drain
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corrected = vector(src_pin.cx(), src_pin.cy() - middle_offset)
|
||||
self.add_via_stack_center(corrected, self.route_layer, self.output_layer)
|
||||
self.add_layout_pin_rect_center(self.bitline_names[0][bl], self.output_layer, corrected )
|
||||
|
||||
#loop
|
||||
|
||||
# self.gnd[0].y()
|
||||
|
||||
|
||||
for col in range(self.column_size):
|
||||
for row in range(self.row_size ):
|
||||
|
||||
#nmos at this position and another nmos further down
|
||||
if self.data[row][col] == 1 :
|
||||
|
||||
next_row = self.get_next_cell_in_bl(row, col)
|
||||
if next_row != -1:
|
||||
|
||||
drain_pin = self.cell_inst[row, col].get_pin("D")
|
||||
source_pin = self.cell_inst[next_row, col].get_pin("S")
|
||||
|
||||
source_pos = source_pin.bc()
|
||||
drain_pos = drain_pin.bc()
|
||||
self.add_path(self.route_layer, [drain_pos, source_pos])
|
||||
|
||||
|
||||
def route_precharge(self):
|
||||
for bl in range(self.column_size):
|
||||
bl_pin = self.cell_list[0][bl].get_pin("S")
|
||||
prechg_pin = "pre_bl{0}_out".format(bl)
|
||||
pre_out_pin = self.precharge_inst.get_pin(prechg_pin)
|
||||
|
||||
bl_start = bl_pin.center()
|
||||
bl_end = vector(bl_start.x, pre_out_pin.cy())
|
||||
|
||||
self.add_segment_center(self.route_layer, bl_start, bl_end)
|
||||
|
||||
def get_next_cell_in_bl(self, row_start, col):
|
||||
for row in range(row_start + 1, self.row_size):
|
||||
|
||||
Reference in New Issue
Block a user