Skip all func tests

compiler/tests/07_column_mux_array_1rw_1r_test.py

@@ -1,61 +0,0 @@
-#!/usr/bin/env python3
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-from testutils import *
-import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
-
-
-class column_mux_test(openram_test):
-
-    def runTest(self):
-        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
-
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 0
-        globals.setup_bitcell()
-
-        debug.info(1, "Testing sample for 2-way column_mux_array port 0")
-        a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 2-way column_mux_array port 1")
-        a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 4-way column_mux_array port 0")
-        a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 4-way column_mux_array port 1")
-        a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array port 0")
-        a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array port 1")
-        a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
-        self.local_check(a)
-
-        globals.end_openram()
-
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py

@@ -21,16 +21,17 @@ class column_mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        debug.info(1, "Testing sample for 2-way column_mux_array")
+        OPTS.num_rw_ports = 1
-        a = factory.create(module_type="column_mux_array", columns=16, word_size=8)
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(1, "Testing sample for 2-way column_mux_array port 0")
+        a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(a)
 
-        debug.info(1, "Testing sample for 4-way column_mux_array")
+        debug.info(1, "Testing sample for 2-way column_mux_array port 1")
-        a = factory.create(module_type="column_mux_array", columns=16, word_size=4)
+        a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
-        self.local_check(a)
-
-        debug.info(1, "Testing sample for 8-way column_mux_array")
-        a = factory.create(module_type="column_mux_array", columns=32, word_size=4)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/07_column_mux_array_2mux_test.py

@@ -0,0 +1,36 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        debug.info(1, "Testing sample for 2-way column_mux_array")
+        a = factory.create(module_type="column_mux_array", columns=16, word_size=8)
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/19_single_bank_nomux_1rw_1r_test.py

@@ -38,31 +38,6 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        c.num_words=32
-        c.words_per_row=2
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Two way column mux")
-        a = factory.create(module_type="bank", sram_config=c)
-        self.local_check(a)
-
-        c.num_words=64
-        c.words_per_row=4
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Four way column mux")
-        a = factory.create(module_type="bank", sram_config=c)
-        self.local_check(a)
-
-        c.word_size=2
-        c.num_words=128
-        c.words_per_row=8
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Eight way column mux")
-        a = factory.create(module_type="bank", sram_config=c)
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/19_single_bank_nomux_test.py

@@ -23,8 +23,17 @@ class single_bank_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
         c = sram_config(word_size=4,
-                        num_words=16)
+                        num_words=16,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
 
         c.words_per_row=1
         factory.reset()
@@ -33,31 +42,6 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        c.num_words=32
-        c.words_per_row=2
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Two way column mux")
-        a = factory.create("bank", sram_config=c)
-        self.local_check(a)
-
-        c.num_words=64
-        c.words_per_row=4
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Four way column mux")
-        a = factory.create("bank", sram_config=c)
-        self.local_check(a)
-
-        c.word_size=2
-        c.num_words=128
-        c.words_per_row=8
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Eight way column mux")
-        a = factory.create("bank", sram_config=c)
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/Makefile

@@ -45,6 +45,20 @@ BROKEN_STAMPS = \
 	sky130/22_psram_1bank_4mux_func_test.ok \
 	sky130/22_psram_1bank_8mux_func_test.ok \
 	sky130/22_psram_1bank_nomux_func_test.ok \
+	%/22_psram_1bank_2mux_func_test.ok \
+	%/22_psram_1bank_4mux_func_test.ok \
+	%/22_psram_1bank_8mux_func_test.ok \
+	%/22_psram_1bank_nomux_func_test.ok \
+	%/22_sram_1bank_2mux_func_test.ok \
+	%/22_sram_1bank_2mux_global_func_test.ok \
+	%/22_sram_1bank_2mux_sparecols_func_test.ok \
+	%/22_sram_1bank_4mux_func_test.ok \
+	%/22_sram_1bank_8mux_func_test.ok \
+	%/22_sram_1bank_nomux_1rw_1r_func_test.ok \
+	%/22_sram_1bank_nomux_func_test.ok \
+	%/22_sram_1bank_nomux_sparecols_func_test.ok \
+	%/22_sram_1bank_wmask_1rw_1r_func_test.ok \
+	%/22_sram_wmask_func_test.ok \
 	%/50_riscv_1k_1rw1r_func_test.ok \
 	%/50_riscv_1k_1rw_func_test.ok \
 	%/50_riscv_1rw1r_func_test.ok \