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Merge branch 'dev' into datasheet_gen

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This commit is contained in:
Jesse Cirimelli-Low
2018-11-10 10:58:35 -08:00
parent 550d5cc729 5cbbd5e4ca
commit 62f8d26ec6
29 changed files with 635 additions and 496 deletions
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compiler/tests/04_precharge_test.py
+4
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@@ -32,6 +32,10 @@ class precharge_test(openram_test):
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
debug.info(2, "Checking precharge for pbitcell (outermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2")
compiler/tests/08_precharge_array_test.py
+10 -6
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@@ -24,18 +24,22 @@ class precharge_test(openram_test):
self.local_check(pc)
# check precharge array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
OPTS.num_w_ports = 0
debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc)
debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(pc)
# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
# pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
# self.local_check(pc)
# debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
# pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
# self.local_check(pc)
globals.end_openram()
compiler/tests/19_psingle_bank_test.py
+10 -4
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@@ -29,27 +29,33 @@ class psingle_bank_test(openram_test):
OPTS.num_r_ports = 0
c = sram_config(word_size=4,
num_words=16)
c.words_per_row=1
debug.info(1, "No column mux")
a = bank(c, name="bank1_1rw_0w_0r_single")
name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
self.local_check(a)
c.num_words=32
c.words_per_row=2
debug.info(1, "Two way column mux")
a = bank(c, name="bank1_1rw_0w_0r_single")
name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
self.local_check(a)
c.num_words=64
c.words_per_row=4
debug.info(1, "Four way column mux")
a = bank(c, name="bank1_1rw_0w_0r_single")
name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
debug.info(1, "Four way column mux")
a = bank(c, name="bank1_1rw_0w_0r_single")
name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
self.local_check(a)
compiler/tests/19_single_bank_test.py
-1
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@@ -38,7 +38,6 @@ class single_bank_test(openram_test):
a = bank(c, name="bank3_single")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
c.word_size=2
c.num_words=128
c.words_per_row=8
compiler/tests/21_ngspice_delay_test.py
+2 -2
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@@ -17,7 +17,7 @@ class timing_sram_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
OPTS.trim_netlist = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -63,7 +63,7 @@ class timing_sram_test(openram_test):
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.644147],
'delay_lh': [1.629815],
'leakage_power': 0.0009299118999999999,
'leakage_power': 0.001542964,
'min_period': 4.688,
'read0_power': [16.28732],
'read1_power': [15.75155],
compiler/tests/testutils.py
+11 -2
View File
@@ -1,12 +1,14 @@
import unittest,warnings
import sys,os,glob,copy
import shutil
sys.path.append(os.path.join(sys.path[0],".."))
from globals import OPTS
import debug
class openram_test(unittest.TestCase):
""" Base unit test that we have some shared classes in. """
def local_drc_check(self, w):
self.reset()
@@ -36,11 +38,17 @@ class openram_test(unittest.TestCase):
import verify
result=verify.run_drc(a.name, tempgds)
if result != 0:
#zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
#debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
#shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
self.fail("DRC failed: {}".format(a.name))
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
if result != 0:
#zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
#debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
#shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
self.fail("LVS mismatch: {}".format(a.name))
if OPTS.purge_temp:
@@ -77,7 +85,8 @@ class openram_test(unittest.TestCase):
if not self.isclose(k,data[k][i],golden_data[k][i],error_tolerance):
data_matches = False
else:
self.isclose(k,data[k],golden_data[k],error_tolerance)
if not self.isclose(k,data[k],golden_data[k],error_tolerance):
data_matches = False
if not data_matches:
import pprint
data_string=pprint.pformat(data)