Merge branch 'dev' into datasheet_gen

compiler/base/design.py

@@ -51,31 +51,36 @@ class design(hierarchy_design):
         self.implant_space = drc("implant_to_implant")
         
     def setup_multiport_constants(self):
-        """ These are contants and lists that aid multiport design """
-        self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
-        self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
-        self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
-        self.num_rw_ports = OPTS.num_rw_ports
+        """ 
+        These are contants and lists that aid multiport design.
+        Ports are always in the order RW, W, R.
+        Port indices start from 0 and increment.
+        A first RW port will have clk0, csb0, web0, addr0, data0
+        A first W port (with no RW ports) will be: clk0, csb0, addr0, data0
+
+        """
+        total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
+
+        # These are the read/write port indices.
+        self.readwrite_ports = []
+        # These are the read/write and write-only port indices
+        self.write_ports = []
+        # These are teh read/write and read-only port indice
+        self.read_ports = []
+        # These are all the ports
+        self.all_ports = list(range(total_ports))
         
-        # Port indices used for data, address, and control signals
-        # Port IDs used to identify port type
-        self.write_index = []
-        self.read_index = []
-        self.port_id = []
         port_number = 0
-        
         for port in range(OPTS.num_rw_ports):
-            self.write_index.append(port_number)
-            self.read_index.append(port_number)
-            self.port_id.append("rw")
+            self.readwrite_ports.append(port_number)
+            self.write_ports.append(port_number)
+            self.read_ports.append(port_number)
             port_number += 1
         for port in range(OPTS.num_w_ports):
-            self.write_index.append(port_number)
-            self.port_id.append("w")
+            self.write_ports.append(port_number)
             port_number += 1
         for port in range(OPTS.num_r_ports):
-            self.read_index.append(port_number)
-            self.port_id.append("r")
+            self.read_ports.append(port_number)
             port_number += 1
 
     def analytical_power(self, proc, vdd, temp, load):

compiler/base/hierarchy_layout.py

@@ -856,10 +856,10 @@ class layout(lef.lef):
             # Remove the net from other constriants in the VCG
             vcg=remove_net_from_graph(net_name, vcg)
             
-            # Add the trunk routes from the bottom up or right to left
+            # Add the trunk routes from the bottom up or the left to right
             if vertical:
                 self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
-                offset -= vector(pitch,0)
+                offset += vector(pitch,0)
             else:
                 self.add_horizontal_trunk_route(pin_list, offset, layer_stack, pitch)
                 offset -= vector(0,pitch)

compiler/base/pin_layout.py

@@ -316,7 +316,43 @@ class pin_layout:
             return [dx,dy]
         else:
             return [0,0]
+
+    def distance(self, other):
+        """ 
+        Calculate the distance to another pin layout.
+        """
+        (r1_ll,r1_ur) = self.rect
+        (r2_ll,r2_ur) = other.rect
+
+        def dist(x1, y1, x2, y2):
+            return sqrt((x2-x1)**2 + (y2-y1)**2)
         
+        left = r2_ur.x < r1_ll.x
+        right = r1_ur.x < r2_ll.x
+        bottom = r2_ur.y < r1_ll.y
+        top = r1_ur.y < r2_ll.y
+
+        if top and left:
+            return dist(r1_ll.x, r1_ur.y, r2_ur.x, r2_ll.y)
+        elif left and bottom:
+            return dist(r1_ll.x, r1_ll.y, r2_ur.x, r2_ur.y)
+        elif bottom and right:
+            return dist(r1_ur.x, r1_ll.y, r2_ll.x, r2_ur.y)
+        elif right and top:
+            return dist(r1_ur.x, r1_ur.y, r2_ll.x, r2_ll.y)
+        elif left:
+            return r1_ll.x - r2_ur.x
+        elif right:
+            return r2_ll.x - r1.ur.x
+        elif bottom:
+            return r1_ll.y - r2_ur.y
+        elif top:
+            return r2_ll.y - r1_ur.y
+        else:
+            # rectangles intersect
+            return 0
+        
+    
     def overlap_length(self, other):
         """ 
         Calculate the intersection segment and determine its length