luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

fix replica col

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2023-08-02 15:19:48 -07:00
parent 5a764c9d43
commit 61cfa55d75
2 changed files with 22 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
-1
View File
@@ -61,7 +61,6 @@ class bitcell_array(bitcell_base_array):
def create_instances(self):
self.cell_inst={}
core_block = [[0 for x in range(1)] for y in range(2)]
# block[row][col]
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
core_block[1][0] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')