updated pbitcell test names

compiler/tests/04_precharge_pbitcell_test.py

@@ -15,12 +15,12 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class precharge_test(openram_test):
+class precharge_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        
+
         # check precharge in multi-port
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
@@ -36,14 +36,14 @@ class precharge_test(openram_test):
         debug.info(2, "Checking precharge for pbitcell (innermost connections)")
         tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(tx)
-        
+
         factory.reset()
         debug.info(2, "Checking precharge for pbitcell (outermost connections)")
         tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(tx)
 
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -17,7 +17,7 @@ import debug
 
 #@unittest.skip("SKIPPING 04_driver_test")
 
-class single_level_column_mux_test(openram_test):
+class single_level_column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/05_replica_pbitcell_array_test.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California 
+# Copyright (c) 2016-2019 Regents of the University of California
 # All rights reserved.
 #
 import unittest
@@ -13,7 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class replica_bitcell_array_test(openram_test):
+class replica_pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -41,7 +41,7 @@ class replica_bitcell_array_test(openram_test):
         debug.info(2, "Testing 4x4 array for pbitcell")
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
         self.local_check(a)
-        
+
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_decoder_test(openram_test):
+class hierarchical_decoder_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -64,7 +64,7 @@ class hierarchical_decoder_test(openram_test):
         self.local_check(a)
 
         globals.end_openram()
-        
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_predecode2x4_test(openram_test):
+class hierarchical_predecode2x4_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_predecode3x8_test(openram_test):
+class hierarchical_predecode3x8_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -14,7 +14,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class single_level_column_mux_test(openram_test):
+class single_level_column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/08_wordline_driver_pbitcell_test.py

@@ -17,7 +17,7 @@ import debug
 
 #@unittest.skip("SKIPPING 04_driver_test")
 
-class wordline_driver_test(openram_test):
+class wordline_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/09_sense_amp_array_test_pbitcell.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class sense_amp_test(openram_test):
+class sense_amp_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class write_driver_test(openram_test):
+class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -17,7 +17,7 @@ from sram_factory import factory
 import debug
 
 
-class write_driver_test(openram_test):
+class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -17,7 +17,7 @@ from sram_factory import factory
 import debug
 
 
-class write_mask_and_array_test(openram_test):
+class write_mask_and_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))