updated pbitcell test names

compiler/tests/04_precharge_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class precharge_test(openram_test):
+class precharge_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -17,7 +17,7 @@ import debug
 
 #@unittest.skip("SKIPPING 04_driver_test")
 
-class single_level_column_mux_test(openram_test):
+class single_level_column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/05_replica_pbitcell_array_test.py

@@ -13,7 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class replica_bitcell_array_test(openram_test):
+class replica_pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_decoder_test(openram_test):
+class hierarchical_decoder_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_predecode2x4_test(openram_test):
+class hierarchical_predecode2x4_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class hierarchical_predecode3x8_test(openram_test):
+class hierarchical_predecode3x8_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -14,7 +14,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class single_level_column_mux_test(openram_test):
+class single_level_column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/08_wordline_driver_pbitcell_test.py

@@ -17,7 +17,7 @@ import debug
 
 #@unittest.skip("SKIPPING 04_driver_test")
 
-class wordline_driver_test(openram_test):
+class wordline_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/09_sense_amp_array_test_pbitcell.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class sense_amp_test(openram_test):
+class sense_amp_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_driver_array_pbitcell_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class write_driver_test(openram_test):
+class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_driver_array_wmask_pbitcell_test.py

@@ -17,7 +17,7 @@ from sram_factory import factory
 import debug
 
 
-class write_driver_test(openram_test):
+class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))

compiler/tests/10_write_mask_and_array_pbitcell_test.py

@@ -17,7 +17,7 @@ from sram_factory import factory
 import debug
 
 
-class write_mask_and_array_test(openram_test):
+class write_mask_and_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))