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updated pbitcell test names
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@@ -17,7 +17,7 @@ from sram_factory import factory
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import debug
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class write_mask_and_array_test(openram_test):
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class write_mask_and_array_pbitcell_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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