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https://github.com/VLSIDA/OpenRAM.git
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updated pbitcell test names
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@@ -15,7 +15,7 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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class hierarchical_decoder_test(openram_test):
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class hierarchical_decoder_pbitcell_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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@@ -64,7 +64,7 @@ class hierarchical_decoder_test(openram_test):
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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