Merge branch 'no_rbl' into delay_ctrl

compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_bothrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,13 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array left and right replica for dp cell")
-        a = factory.create(module_type="capped_replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           left_rbl=[0],
-                           right_rbl=[1])
+        debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with both replica columns")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class capped_replica_bitcell_array_dummies_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with dummy rows only")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class capped_replica_bitcell_array_dummies_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="capped_replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           left_rbl=[0])
+        debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with left replica column")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
         self.local_check(a)
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_test(openram_test):
+class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,8 +23,9 @@ class capped_replica_bitcell_array_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array for bitcell")
+        debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column")
         a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)
 

compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_norbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 non-replica array for dp cell")
-        a = factory.create(module_type="capped_replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1])
+        debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell without replica columns or dummy rows")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_test(openram_test):
+class capped_replica_bitcell_array_norbl_1rw_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,9 +23,10 @@ class capped_replica_bitcell_array_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class capped_replica_bitcell_array_1rw_1r_test(openram_test):
+class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="capped_replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           right_rbl=[1])
+        debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with right replica column")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
         self.local_check(a)
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_1rw_1r_test(openram_test):
+class replica_bitcell_array_bothrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,13 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array left and right replica for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           left_rbl=[0],
-                           right_rbl=[1])
+        debug.info(2, "Testing 4x4 replica array for 1rw1r cell with both replica columns")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_bitcell_array_dummies_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 replica array for 1rw1r cell with dummy rows only")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_bitcell_array_dummies_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only")
+        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_1rw_1r_test(openram_test):
+class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           left_rbl=[0])
+        debug.info(2, "Testing 4x4 replica array for 1rw1r cell with left replica column")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
         self.local_check(a)
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_test(openram_test):
+class replica_bitcell_array_leftrbl_1rw_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,8 +23,9 @@ class replica_bitcell_array_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array for bitcell")
+        debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column")
         a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)
 

compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_1rw_1r_test(openram_test):
+class replica_bitcell_array_norbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 non-replica array for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1])
+        debug.info(2, "Testing 4x4 replica array for 1rw1r cell without replica columns or dummy rows")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_test(openram_test):
+class replica_bitcell_array_norbl_1rw_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,9 +23,10 @@ class replica_bitcell_array_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row")
+        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py

@@ -14,7 +14,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-class replica_bitcell_array_1rw_1r_test(openram_test):
+class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           right_rbl=[1])
+        debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column")
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
         self.local_check(a)
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/15_global_bitcell_array_norbl_1rw_1r_test.py

@@ -1,9 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 import sys, os
@@ -11,24 +9,24 @@ import unittest
 from testutils import *
 
 import openram
-from openram.sram_factory import factory
 from openram import debug
+from openram.sram_factory import factory
 from openram import OPTS
 
 
-# @unittest.skip("SKIPPING 05_global_bitcell_array_test")
-class global_bitcell_array_test(openram_test):
+class global_bitcell_array_norbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
 
-        # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
-        # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
-        # self.local_check(a)
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
-        a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4)
+        debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell without replica columns")
+        a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[0, 0], left_rbl=[], right_rbl=[])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/15_global_bitcell_array_norbl_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class global_bitcell_array_norbl_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell without replica column")
+        a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[0, 0], left_rbl=[])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class global_bitcell_array_rbl_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell with replica columns")
+        a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_global_bitcell_array_rbl_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class global_bitcell_array_rbl_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell with left replica column")
+        a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[1, 0], left_rbl=[0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_1rw_1r_test.py

@@ -1,55 +0,0 @@
-#!/usr/bin/env python3
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-import sys, os
-import unittest
-from testutils import *
-
-import openram
-from openram import debug
-from openram.sram_factory import factory
-from openram import OPTS
-
-
-# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
-class local_bitcell_array_1rw_1r_test(openram_test):
-
-    def runTest(self):
-        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        openram.init_openram(config_file, is_unit_test=True)
-
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 0
-        openram.setup_bitcell()
-
-        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
-        self.local_check(a)
-
-        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
-        self.local_check(a)
-
-        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
-        self.local_check(a)
-
-        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
-        self.local_check(a)
-
-        openram.end_openram()
-
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = openram.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py

@@ -1,9 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 import sys, os
@@ -16,19 +14,19 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
-class local_bitcell_array_test(openram_test):
+class local_bitcell_array_bothrbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
 
-        debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
-        self.local_check(a)
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
-        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
+        debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with both replica columns")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_dummies_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with dummy rows only")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_dummies_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_dummies_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with dummy row only")
+        a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_leftrbl_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with left replica column")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_leftrbl_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with left replica column")
+        a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_norbl_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell without replica columns or dummy rows")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_norbl_1rw_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_norbl_1rw_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 7x5 local bitcell array for 1rw cell without replica column or dummy row")
+        a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[0, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class local_bitcell_array_rightrbl_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with right replica column")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py

@@ -16,25 +16,27 @@ from openram.sram_factory import factory
 from openram import OPTS
 
 
-# @unittest.skip("SKIPPING 05_global_bitcell_array_test")
-class global_bitcell_array_test(openram_test):
+class single_bank_nomux_norbl_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         openram.init_openram(config_file, is_unit_test=True)
+        from openram import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
         openram.setup_bitcell()
 
-        debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r")
-        a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
-        self.local_check(a)
+        c = sram_config(word_size=4,
+                        num_words=16)
 
-        # debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
-        # a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
-        # self.local_check(a)
+        c.words_per_row=1
+        OPTS.control_logic = "control_logic_delay"
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create(module_type="bank", sram_config=c)
+        self.local_check(a)
 
         openram.end_openram()
 

compiler/tests/19_single_bank_nomux_norbl_test.py

@@ -0,0 +1,54 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class single_bank_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import sram_config
+
+        if OPTS.tech_name == "sky130":
+            num_spare_rows = 1
+            num_spare_cols = 1
+        else:
+            num_spare_rows = 0
+            num_spare_cols = 0
+
+        c = sram_config(word_size=4,
+                        num_words=16,
+                        num_spare_cols=num_spare_cols,
+                        num_spare_rows=num_spare_rows)
+
+        c.words_per_row=1
+        OPTS.control_logic = "control_logic_delay"
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py

@@ -0,0 +1,58 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class sram_1bank_nomux_norbl_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import sram_config
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        c = sram_config(word_size=4,
+                        num_words=16,
+                        num_banks=1)
+
+        c.words_per_row=1
+        OPTS.control_logic = "control_logic_delay"
+        c.recompute_sizes()
+        debug.info(1, "Layout test for {}rw,{}r,{}w sram "
+                   "with {} bit words, {} words, {} words per "
+                   "row, {} banks".format(OPTS.num_rw_ports,
+                                          OPTS.num_r_ports,
+                                          OPTS.num_w_ports,
+                                          c.word_size,
+                                          c.num_words,
+                                          c.words_per_row,
+                                          c.num_banks))
+        a = factory.create(module_type="sram", sram_config=c)
+        self.local_check(a, final_verification=True)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())