mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-01 10:39:35 +02:00
New power strapping mostly working.
Each module uses M3/M4 power straps with pins on the ends. Works in all technologies for a single no mux, dual port SRAM.
This commit is contained in:
mrg
@@ -305,19 +305,18 @@ class replica_bitcell_array(bitcell_base_array):
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def create_layout(self):
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# We will need unused wordlines grounded, so we need to know their layer
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# and create a space on the left and right for the vias to connect to ground
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pin = self.cell.get_pin(self.cell.get_all_wl_names()[0])
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pin_layer = pin.layer
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self.unused_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
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self.unused_offset = vector(self.unused_pitch, 0)
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# This creates space for the unused wordline connections as well as the
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# row-based or column based power and ground lines.
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self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2]))
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self.unused_offset = vector(2 * self.horizontal_pitch, 2 * self.vertical_pitch)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the main array at (self.unused_pitch, 0) to start
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# Everything is computed with the main array
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self.bitcell_array_inst.place(offset=self.unused_offset)
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self.add_replica_columns()
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@@ -336,6 +335,8 @@ class replica_bitcell_array(bitcell_base_array):
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self.add_layout_pins()
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self.route_supplies()
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self.route_unused_wordlines()
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self.add_boundary()
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@@ -458,23 +459,82 @@ class replica_bitcell_array(bitcell_base_array):
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width=pin.width(),
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height=self.height)
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if OPTS.tech_name=="sky130" or OPTS.experimental_power:
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self.route_vertical_pins(name="gnd", insts=self.replica_col_insts)
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self.route_horizontal_pins(name="vdd", insts=self.dummy_row_insts)
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else:
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# vdd/gnd are only connected in the perimeter cells
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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def route_supplies(self):
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for pin_name in self.supplies:
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for inst in supply_insts:
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.copy_power_pin(pin)
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# vdd/gnd are only connected in the perimeter cells
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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vdd_leftx = 0
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vdd_rightx = 0
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gnd_leftx = 0
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gnd_rightx = 0
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for inst in supply_insts:
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for pin in inst.get_pins("vdd"):
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(vdd_leftx, vdd_rightx) = self.connect_pin(pin, 2.5)
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for pin in inst.get_pins("gnd"):
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(gnd_leftx, gnd_rightx) = self.connect_pin(pin)
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self.add_layout_end_pin_segment_center(text="vdd",
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layer=self.supply_stack[2],
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start=vector(vdd_leftx, 0),
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end=vector(vdd_leftx, self.height))
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self.add_layout_end_pin_segment_center(text="vdd",
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layer=self.supply_stack[2],
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start=vector(vdd_rightx, 0),
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end=vector(vdd_rightx, self.height))
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self.add_layout_end_pin_segment_center(text="gnd",
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layer=self.supply_stack[2],
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start=vector(gnd_leftx, 0),
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end=vector(gnd_leftx, self.height))
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self.add_layout_end_pin_segment_center(text="gnd",
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layer=self.supply_stack[2],
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start=vector(gnd_rightx, 0),
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end=vector(gnd_rightx, self.height))
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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# This grounds all the dummy row word lines
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap_top.get_wordline_names():
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pin = inst.get_pin(wl_name)
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self.connect_pin(pin)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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pin = inst.get_pin(pin_name)
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self.connect_pin(pin)
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def connect_pin(self, pin, offset_multiple=1):
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pin_layer = pin.layer
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left_pin_loc = vector(self.dummy_col_insts[0].lx(), pin.cy())
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right_pin_loc = vector(self.dummy_col_insts[1].rx(), pin.cy())
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# Place the pins a track outside of the array
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left_loc = left_pin_loc - vector(offset_multiple * self.horizontal_pitch, 0)
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right_loc = right_pin_loc + vector(offset_multiple * self.horizontal_pitch, 0)
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self.add_via_stack_center(offset=left_loc,
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from_layer=pin_layer,
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to_layer=self.supply_stack[2],
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directions=("H", "H"))
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self.add_via_stack_center(offset=right_loc,
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from_layer=pin_layer,
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to_layer=self.supply_stack[2],
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directions=("H", "H"))
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# Add a path to connect to the array
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self.add_path(pin_layer, [left_loc, right_loc])
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return (left_loc.x, right_loc.x)
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for inst in self.replica_col_insts:
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if inst:
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self.copy_layout_pin(inst, pin_name)
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def analytical_power(self, corner, load):
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@@ -494,34 +554,6 @@ class replica_bitcell_array(bitcell_base_array):
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def route_unused_wordlines(self):
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""" Connect the unused RBL and dummy wordlines to gnd """
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# This grounds all the dummy row word lines
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for inst in self.dummy_row_insts:
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for wl_name in self.col_cap_top.get_wordline_names():
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self.ground_pin(inst, wl_name)
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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self.ground_pin(inst, pin_name)
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def ground_pin(self, inst, name):
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pin = inst.get_pin(name)
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pin_layer = pin.layer
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left_pin_loc = vector(self.dummy_col_insts[0].lx(), pin.cy())
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right_pin_loc = vector(self.dummy_col_insts[1].rx(), pin.cy())
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# Place the pins a track outside of the array
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left_loc = left_pin_loc - vector(self.unused_pitch, 0)
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right_loc = right_pin_loc + vector(self.unused_pitch, 0)
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self.add_power_pin("gnd", left_loc, directions=("H", "H"))
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self.add_power_pin("gnd", right_loc, directions=("H", "H"))
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# Add a path to connect to the array
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self.add_path(pin_layer, [left_loc, right_loc], width=pin.height())
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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