luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

New power strapping mostly working.

Browse Source 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
This commit is contained in:
mrg
2022-04-05 13:51:55 -07:00
parent 68d0a56423
commit 5e546ee974
17 changed files with 512 additions and 286 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/precharge_array.py
+2 -6
View File
@@ -83,7 +83,7 @@ class precharge_array(design.design):
def add_layout_pins(self):
en_pin = self.pc_cell.get_pin("en_bar")
self.route_horizontal_pins("en_bar", layer=self.en_bar_layer)
self.route_horizontal_pins("en_bar", layer=self.en_bar_layer, num_pins=1)
for inst in self.local_insts:
self.add_via_stack_center(from_layer=en_pin.layer,
to_layer=self.en_bar_layer,
@@ -95,11 +95,7 @@ class precharge_array(design.design):
self.copy_layout_pin(inst, "br", "br_{0}".format(i))
def route_supplies(self):
if OPTS.tech_name=="sky130" or OPTS.experimental_power:
self.route_horizontal_pins("vdd")
else:
for inst in self.local_insts:
self.copy_layout_pin(inst, "vdd")
self.route_horizontal_pins("vdd")
def create_insts(self):
"""Creates a precharge array by horizontally tiling the precharge cell"""