New power strapping mostly working.

Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.

compiler/modules/dummy_array.py

@@ -36,6 +36,8 @@ class dummy_array(bitcell_base_array):
 
         self.add_layout_pins()
 
+        self.route_supplies()
+
         self.add_boundary()
 
         self.DRC_LVS()
@@ -98,6 +100,8 @@ class dummy_array(bitcell_base_array):
                                         width=self.width,
                                         height=wl_pin.height())
 
+    def route_supplies(self):
+
         # Copy a vdd/gnd layout pin from every cell
         for row in range(self.row_size):
             for col in range(self.column_size):