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New power strapping mostly working.

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Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
This commit is contained in:
mrg
2022-04-05 13:51:55 -07:00
parent 68d0a56423
commit 5e546ee974
17 changed files with 512 additions and 286 deletions
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compiler/modules/delay_chain.py
+5 -3
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@@ -177,9 +177,11 @@ class delay_chain(design.design):
# The routing to connect the loads is over the first and last cells
# We have an even number of drivers and must only do every other
# supply rail
if OPTS.experimental_power:
self.route_horizontal_pins("vdd")
self.route_horizontal_pins("gnd")
if True or OPTS.experimental_power:
left_load_insts = [self.load_inst_map[x][0] for x in self.driver_inst_list]
right_load_insts = [self.load_inst_map[x][-1] for x in self.driver_inst_list]
self.route_vertical_pins("vdd", left_load_insts, xside="lx")
self.route_vertical_pins("gnd", right_load_insts, xside="rx")
else:
for inst in self.driver_inst_list:
load_list = self.load_inst_map[inst]