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modules/port_data: Add get_bl/br_name method

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if we rely on the names of the submodules (sense_amp_array,
write_driver_array, etc.) for port_data's pins, we get into trouble on
multiport SRAMs. To avoid this we use explicit names for br/bl depending
on the port number in port_data. Now each submodule does no longer need to
figure out the right name depending on the port number.

Signed-off-by: Bastian Koppelmann <[email protected]>
This commit is contained in:
Bastian Koppelmann
2020-02-17 14:18:32 +01:00
parent 87b5a48f9e
commit 5e1f64c8f9
5 changed files with 37 additions and 52 deletions
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compiler/modules/write_driver_array.py
+4 -10
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@@ -37,19 +37,13 @@ class write_driver_array(design.design):
if not OPTS.netlist_only:
self.create_layout()
def get_bl_name(self, port=0):
def get_bl_name(self):
bl_name = self.driver.get_bl_names()
if len(self.all_ports) == 1:
return bl_name
else:
return bl_name + "{}".format(port)
return bl_name
def get_br_name(self, port=0):
def get_br_name(self):
br_name = self.driver.get_br_names()
if len(self.all_ports) == 1:
return br_name
else:
return br_name + "{}".format(port)
return br_name
def create_netlist(self):
self.add_modules()