mirror of https://github.com/VLSIDA/OpenRAM.git
remove whitespace
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@ -53,8 +53,8 @@ class dummy_array(bitcell_base_array):
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""" Create the module instances used in this design """
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""" Create the module instances used in this design """
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self.cell_inst={}
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self.cell_inst={}
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core_block = [[0 for x in range(1)] for y in range(2)]
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core_block = [[0 for x in range(1)] for y in range(2)]
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core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[0][(0+self.mirror) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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core_block[0][(1+self.mirror) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
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self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
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@ -1,3 +1,8 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram import debug
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from openram.base.geometry import instance,geometry
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from openram.base.geometry import instance,geometry
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from typing import List
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from typing import List
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