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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
Fixed known typos of the word transition.
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@@ -299,13 +299,13 @@ class setup_hold():
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for self.constrained_input_slew in constrained_slews:
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debug.info(1, "Clock slew: {0} Data slew: {1}".format(self.related_input_slew,self.constrained_input_slew))
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LH_setup_time = self.setup_LH_time()
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debug.info(1, " Setup Time for low_to_high transistion: {0}".format(LH_setup_time))
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debug.info(1, " Setup Time for low_to_high transition: {0}".format(LH_setup_time))
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HL_setup_time = self.setup_HL_time()
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debug.info(1, " Setup Time for high_to_low transistion: {0}".format(HL_setup_time))
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debug.info(1, " Setup Time for high_to_low transition: {0}".format(HL_setup_time))
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LH_hold_time = self.hold_LH_time()
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debug.info(1, " Hold Time for low_to_high transistion: {0}".format(LH_hold_time))
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debug.info(1, " Hold Time for low_to_high transition: {0}".format(LH_hold_time))
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HL_hold_time = self.hold_HL_time()
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debug.info(1, " Hold Time for high_to_low transistion: {0}".format(HL_hold_time))
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debug.info(1, " Hold Time for high_to_low transition: {0}".format(HL_hold_time))
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LH_setup.append(LH_setup_time)
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HL_setup.append(HL_setup_time)
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LH_hold.append(LH_hold_time)
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@@ -43,8 +43,8 @@ class ms_flop(design.design):
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transistion_prob = spice["flop_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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@@ -279,5 +279,5 @@ class pinv(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["inv_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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transition_prob = spice["inv_transition_prob"]
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return transition_prob*(c_load + c_para)
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@@ -240,5 +240,5 @@ class pnand2(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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transition_prob = spice["nand2_transition_prob"]
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return transition_prob*(c_load + c_para)
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@@ -259,5 +259,5 @@ class pnand3(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand3_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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transition_prob = spice["nand3_transition_prob"]
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return transition_prob*(c_load + c_para)
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@@ -237,6 +237,6 @@ class pnor2(pgate.pgate):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nor2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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transition_prob = spice["nor2_transition_prob"]
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return transition_prob*(c_load + c_para)
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