mirror of https://github.com/VLSIDA/OpenRAM.git
Revert "Fix whitespace"
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parent
f1e452c8e3
commit
5d6e56763f
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@ -220,3 +220,4 @@ class lef:
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round(item[1],
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self.round_grid)))
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self.lef.write(" ;\n")
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@ -153,3 +153,4 @@ class timing_graph():
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""" override print function output """
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return str(self)
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@ -118,3 +118,5 @@ class cacti(simulation):
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debug.info(1, "Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
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return power
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@ -40,3 +40,4 @@ class linear_regression(regression_model):
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pred = model.predict(features)
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return pred
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@ -211,3 +211,4 @@ class voltage_at_measure(spice_measurement):
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meas_name = self.name
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targ_name = self.targ_name_no_port
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return (meas_name, targ_name, time_at)
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@ -448,3 +448,6 @@ class model_check(delay):
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name_dict[self.sae_model_name] = name_dict["sae_measures"]
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return name_dict
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@ -41,3 +41,4 @@ class neural_network(regression_model):
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pred = model.predict(features)
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reshape_pred = np.reshape(pred, (len(pred),1))
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return reshape_pred
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@ -205,3 +205,4 @@ class regression_model(simulation):
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OPTS.model_dict[model_name+"_coef"] = list(model.coef_[0])
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debug.info(1,"Coefs of {}:{}".format(model_name,OPTS.model_dict[model_name+"_coef"]))
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OPTS.model_dict[model_name+"_intercept"] = float(model.intercept_)
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@ -134,3 +134,4 @@ def bp():
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and whenever you encounter the debug.bp() they won't be "reset".
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"""
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pass
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@ -290,3 +290,4 @@ class cell_properties():
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@property
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def row_cap_2port(self):
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return self._row_cap_2port
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@ -267,3 +267,27 @@ if __name__ == "__main__":
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input_dir_path = sys.argv[1]
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out_path = sys.argv[2]
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gen_model_csv(input_dir_path, out_path)
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@ -213,3 +213,8 @@ class grid:
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"""
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path.set_path(False)
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path.set_blocked(True)
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@ -49,3 +49,4 @@ class grid_cell:
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type_string += "P"
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return type_string
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@ -102,3 +102,5 @@ class signal_escape_router(router):
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# breakpoint()
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self.write_debug_gds("debug_route.gds", True)
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@ -77,3 +77,5 @@ class supply_grid(signal_grid):
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wave = wave_path.neighbor(direct)
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return wave_path
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@ -392,3 +392,4 @@ class supply_grid_router(router):
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debug.info(4, "Blocking supply rail")
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for rail_name in self.supply_rail_tracks:
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self.rg.set_blocked(self.supply_rail_tracks[rail_name])
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@ -28,7 +28,6 @@ class code_format_test(openram_test):
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continue
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errors += check_file_format_tab(code)
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errors += check_file_format_carriage(code)
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errors += check_file_format_whitespace(code)
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for code in source_codes:
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if re.search("gdsMill", code):
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@ -52,7 +51,7 @@ def setup_files(path):
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files = []
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for (dir, _, current_files) in os.walk(path):
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for f in current_files:
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files.append(os.path.join(dir, f))
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files.append(os.getenv("OPENRAM_HOME"))
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nametest = re.compile("\.py$", re.IGNORECASE)
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select_files = list(filter(nametest.search, files))
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return select_files
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@ -93,35 +92,13 @@ def check_file_format_carriage(file_name):
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if len(key_positions)>10:
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line_numbers = key_positions[:10] + [" ..."]
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else:
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line_numbers = key_positions
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line_numbers = key_positoins
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debug.info(0, '\nFound ' + str(len(key_positions)) + ' carriage returns in ' +
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str(file_name) + ' (lines ' + ",".join(str(x) for x in line_numbers) + ')')
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f.close()
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return len(key_positions)
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def check_file_format_whitespace(file_name):
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"""
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Check if file contains a line with whitespace at the end
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and return the number of these lines.
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"""
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f = open(file_name, "r")
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key_positions = []
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for num, line in enumerate(f.readlines()):
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if re.match(r".*[ \t]$", line):
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key_positions.append(num)
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if len(key_positions) > 0:
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if len(key_positions) > 10:
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line_numbers = key_positions[:10] + [" ..."]
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else:
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line_numbers = key_positions
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debug.info(0, "\nFound " + str(len(key_positions)) + " ending whitespace in " +
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str(file_name) + " (lines " + ",".join(str(x) for x in line_numbers) + ")")
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f.close()
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return len(key_positions)
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def check_print_output(file_name):
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"""Check if any files (except debug.py) call the _print_ function. We should
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use the debug output with verbosity instead!"""
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