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Fix p_en_bar at top level. Change default scn4m period to 10ns.

This commit is contained in:
Matt Guthaus 2018-11-27 14:44:55 -08:00
parent c45f990413
commit 5d59863efc
2 changed files with 4 additions and 4 deletions
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6
compiler/sram_base.py
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@ -143,7 +143,7 @@ class sram_base(design):
self.control_bus_names[port] = ["clk_buf{}".format(port)] self.control_bus_names[port] = ["clk_buf{}".format(port)]
wen = "w_en{}".format(port) wen = "w_en{}".format(port)
sen = "s_en{}".format(port) sen = "s_en{}".format(port)
pen = "p_en{}".format(port) pen = "p_en_bar{}".format(port)
if self.port_id[port] == "r": if self.port_id[port] == "r":
self.control_bus_names[port].extend([sen, pen]) self.control_bus_names[port].extend([sen, pen])
elif self.port_id[port] == "w": elif self.port_id[port] == "w":
@ -293,7 +293,7 @@ class sram_base(design):
for port in self.read_ports: for port in self.read_ports:
temp.append("s_en{0}".format(port)) temp.append("s_en{0}".format(port))
for port in self.read_ports: for port in self.read_ports:
temp.append("p_en{0}".format(port)) temp.append("p_en_bar{0}".format(port))
for port in self.write_ports: for port in self.write_ports:
temp.append("w_en{0}".format(port)) temp.append("w_en{0}".format(port))
for port in self.all_ports: for port in self.all_ports:
@ -419,7 +419,7 @@ class sram_base(design):
if port in self.write_ports: if port in self.write_ports:
temp.append("w_en{}".format(port)) temp.append("w_en{}".format(port))
if port in self.read_ports: if port in self.read_ports:
temp.append("p_en{}".format(port)) temp.append("p_en_bar{}".format(port))
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)

2
technology/scn4m_subm/tech/tech.py
View File

@ -240,7 +240,7 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"
#spice stimulus related variables #spice stimulus related variables
spice["feasible_period"] = 5 # estimated feasible period in ns spice["feasible_period"] = 10 # estimated feasible period in ns
spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
spice["rise_time"] = 0.05 # rise time in [Nano-seconds] spice["rise_time"] = 0.05 # rise time in [Nano-seconds]