mirror of https://github.com/VLSIDA/OpenRAM.git
Detect via size for power ring.
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@ -639,6 +639,7 @@ class layout(lef.lef):
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if c.second_layer_width < self.supply_rail_width and c.second_layer_height < self.supply_rail_width:
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if c.second_layer_width < self.supply_rail_width and c.second_layer_height < self.supply_rail_width:
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self.supply_vias += 1
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self.supply_vias += 1
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else:
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else:
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self.supply_vias -= 1
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break
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break
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via_points = [vector(self.left_gnd_x_center, self.bottom_gnd_y_center),
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via_points = [vector(self.left_gnd_x_center, self.bottom_gnd_y_center),
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@ -147,7 +147,8 @@ class bank(design.design):
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# Width for the vdd/gnd rails
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# Width for the vdd/gnd rails
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self.supply_rail_width = 4*self.m2_width
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self.supply_rail_width = 4*self.m2_width
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self.supply_rail_pitch = self.supply_rail_width + 2*self.m2_space
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# FIXME: This spacing should be width dependent...
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self.supply_rail_pitch = self.supply_rail_width + 4*self.m2_space
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# Number of control lines in the bus
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# Number of control lines in the bus
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self.num_control_lines = 6
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self.num_control_lines = 6
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@ -169,7 +170,8 @@ class bank(design.design):
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self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
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self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
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# The width of this bus is needed to place other modules (e.g. decoder)
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# The width of this bus is needed to place other modules (e.g. decoder)
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self.central_bus_width = self.m2_pitch * self.num_control_lines
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# A width on each side too
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self.central_bus_width = self.m2_pitch * self.num_control_lines + 2*self.m2_width
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@ -533,7 +535,7 @@ class bank(design.design):
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# and control lines.
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# and control lines.
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# The bank is at (0,0), so this is to the left of the y-axis.
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# The bank is at (0,0), so this is to the left of the y-axis.
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# 2 pitches on the right for vias/jogs to access the inputs
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# 2 pitches on the right for vias/jogs to access the inputs
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control_bus_x_offset = -self.m2_pitch * self.num_control_lines
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control_bus_x_offset = -self.m2_pitch * self.num_control_lines - self.m2_width
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# Track the bus offsets for other modules to access
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# Track the bus offsets for other modules to access
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self.bus_xoffset = {}
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self.bus_xoffset = {}
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