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Update remaining SCMOS golden lib files.

This commit is contained in:
Matt Guthaus 2018-07-27 09:44:12 -07:00
parent 6b967c08dd
commit 5b2cb6a95e
3 changed files with 55 additions and 47 deletions
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2
compiler/tests/23_lib_sram_test.py
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@ -48,7 +48,7 @@ class lib_test(openram_test):
for filename in lib_files: for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename) libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename) golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.40) self.assertTrue(self.isapproxdiff(libname,golden,0.40))
reload(characterizer) reload(characterizer)
globals.end_openram() globals.end_openram()

58
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
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@ -78,27 +78,31 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 134589.78; area : 142800.38999999998;
leakage_power () { leakage_power () {
when : "CSb"; when : "CSb";
value : 0.0004764706; value : 0.0252988;
} }
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DATA){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : in;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605; min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
bus(DOUT){
bus_type : DATA;
direction : out;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DOUT[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -130,26 +134,26 @@ cell (sram_2_16_1_scn3me_subm){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : rising_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.474, 0.52, 0.888",\ values("0.945, 0.976, 1.139",\
"0.477, 0.522, 0.892",\ "0.948, 0.98, 1.143",\
"0.517, 0.561, 0.929"); "1.003, 1.036, 1.202");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.582, 0.658, 1.26",\ values("11.211, 11.266, 11.754",\
"0.586, 0.661, 1.262",\ "11.212, 11.267, 11.755",\
"0.626, 0.7, 1.298"); "11.264, 11.319, 11.806");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.155, 0.233, 1.087",\ values("0.605, 0.629, 0.98",\
"0.156, 0.235, 1.086",\ "0.605, 0.629, 0.979",\
"0.16, 0.239, 1.086"); "0.604, 0.628, 0.973");
} }
fall_transition(CELL_TABLE) { fall_transition(CELL_TABLE) {
values("0.277, 0.356, 1.502",\ values("11.17, 11.175, 1.284",\
"0.278, 0.358, 1.501",\ "11.167, 11.173, 1.284",\
"0.279, 0.363, 1.5"); "11.173, 11.179, 11.473");
} }
} }
} }
@ -298,19 +302,19 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){ internal_power(){
when : "!CSb & clk & !WEb"; when : "!CSb & clk & !WEb";
rise_power(scalar){ rise_power(scalar){
values("4.92665"); values("2.1762222222222225");
} }
fall_power(scalar){ fall_power(scalar){
values("4.92665"); values("2.1762222222222225");
} }
} }
internal_power(){ internal_power(){
when : "!CSb & !clk & WEb"; when : "!CSb & !clk & WEb";
rise_power(scalar){ rise_power(scalar){
values("5.74515833333"); values("2.167955555555556");
} }
fall_power(scalar){ fall_power(scalar){
values("5.74515833333"); values("2.167955555555556");
} }
} }
internal_power(){ internal_power(){
@ -326,20 +330,20 @@ cell (sram_2_16_1_scn3me_subm){
timing_type :"min_pulse_width"; timing_type :"min_pulse_width";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("1.875"); values("9.6875");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("1.875"); values("9.6875");
} }
} }
timing(){ timing(){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("3.75"); values("19.375");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("3.75"); values("19.375");
} }
} }
} }

42
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
View File

@ -78,27 +78,31 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true; dont_use : true;
map_only : true; map_only : true;
dont_touch : true; dont_touch : true;
area : 134589.78; area : 142800.38999999998;
leakage_power () { leakage_power () {
when : "CSb"; when : "CSb";
value : 0.000173; value : 0.000168;
} }
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DATA){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : inout; direction : in;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605; min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
bus(DOUT){
bus_type : DATA;
direction : out;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){ memory_read(){
address : ADDR; address : ADDR;
} }
pin(DATA[1:0]){ pin(DOUT[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk"; related_pin : "clk";
@ -130,16 +134,16 @@ cell (sram_2_16_1_scn3me_subm){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk"; related_pin : "clk";
timing_type : falling_edge; timing_type : rising_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.556, 0.603, 1.044",\ values("0.54, 0.587, 1.028",\
"0.556, 0.603, 1.044",\ "0.54, 0.587, 1.028",\
"0.556, 0.603, 1.044"); "0.54, 0.587, 1.028");
} }
cell_fall(CELL_TABLE) { cell_fall(CELL_TABLE) {
values("0.556, 0.603, 1.044",\ values("0.54, 0.587, 1.028",\
"0.556, 0.603, 1.044",\ "0.54, 0.587, 1.028",\
"0.556, 0.603, 1.044"); "0.54, 0.587, 1.028");
} }
rise_transition(CELL_TABLE) { rise_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\ values("0.024, 0.081, 0.61",\
@ -298,19 +302,19 @@ cell (sram_2_16_1_scn3me_subm){
internal_power(){ internal_power(){
when : "!CSb & clk & !WEb"; when : "!CSb & clk & !WEb";
rise_power(scalar){ rise_power(scalar){
values("10.9314668117"); values("10.559086132533329");
} }
fall_power(scalar){ fall_power(scalar){
values("10.9314668117"); values("10.559086132533329");
} }
} }
internal_power(){ internal_power(){
when : "!CSb & !clk & WEb"; when : "!CSb & !clk & WEb";
rise_power(scalar){ rise_power(scalar){
values("10.9314668117"); values("10.559086132533329");
} }
fall_power(scalar){ fall_power(scalar){
values("10.9314668117"); values("10.559086132533329");
} }
} }
internal_power(){ internal_power(){
@ -336,10 +340,10 @@ cell (sram_2_16_1_scn3me_subm){
timing_type :"minimum_period"; timing_type :"minimum_period";
related_pin : clk; related_pin : clk;
rise_constraint(scalar) { rise_constraint(scalar) {
values("0.0"); values("0");
} }
fall_constraint(scalar) { fall_constraint(scalar) {
values("0.0"); values("0");
} }
} }
} }