luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

PEP8 Formatting

This commit is contained in:
mrg 2020-03-05 16:13:49 -08:00
parent ad98137cd4
commit 5b23653369
1 changed files with 78 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
compiler/sram/sram_1bank.py
View File

@ -95,7 +95,6 @@ class sram_1bank(sram_base):
wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0) wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
data_pos[port] = vector(self.bank.bank_array_ll.x, 0) data_pos[port] = vector(self.bank.bank_array_ll.x, 0)
# Add the col address flops below the bank to the left of the lower-left of bank array # Add the col address flops below the bank to the left of the lower-left of bank array
if self.col_addr_dff: if self.col_addr_dff:
if self.write_size: if self.write_size:
@ -159,10 +158,9 @@ class sram_1bank(sram_base):
# This includes 2 M2 pitches for the row addr clock line # This includes 2 M2 pitches for the row addr clock line
control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch, control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch,
self.bank.bank_array_ur.y + self.control_logic_insts[port].height - self.bank.bank_array_ur.y + self.control_logic_insts[port].height - \
(self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y) (self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y)
+ 2 * self.bank.m2_gap) + 2 * self.bank.m2_gap)
#import pdb; pdb.set_trace()
self.control_logic_insts[port].place(control_pos[port], mirror="XY") self.control_logic_insts[port].place(control_pos[port], mirror="XY")
# The row address bits are placed above the control logic aligned on the left. # The row address bits are placed above the control logic aligned on the left.
@ -172,7 +170,6 @@ class sram_1bank(sram_base):
row_addr_pos[port] = vector(x_offset, y_offset) row_addr_pos[port] = vector(x_offset, y_offset)
self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY")
def add_layout_pins(self): def add_layout_pins(self):
""" """
Add the top-level pins for a single bank SRAM with control. Add the top-level pins for a single bank SRAM with control.
@ -180,27 +177,38 @@ class sram_1bank(sram_base):
for port in self.all_ports: for port in self.all_ports:
# Connect the control pins as inputs # Connect the control pins as inputs
for signal in self.control_logic_inputs[port] + ["clk"]: for signal in self.control_logic_inputs[port] + ["clk"]:
self.copy_layout_pin(self.control_logic_insts[port], signal, signal+"{}".format(port)) self.copy_layout_pin(self.control_logic_insts[port],
signal,
signal + "{}".format(port))
if port in self.read_ports: if port in self.read_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
self.copy_layout_pin(self.bank_inst, "dout{0}_{1}".format(port,bit), "dout{0}[{1}]".format(port,bit)) self.copy_layout_pin(self.bank_inst,
"dout{0}_{1}".format(port, bit),
"dout{0}[{1}]".format(port, bit))
# Lower address bits # Lower address bits
for bit in range(self.col_addr_size): for bit in range(self.col_addr_size):
self.copy_layout_pin(self.col_addr_dff_insts[port], "din_{}".format(bit),"addr{0}[{1}]".format(port,bit)) self.copy_layout_pin(self.col_addr_dff_insts[port],
"din_{}".format(bit),
"addr{0}[{1}]".format(port, bit))
# Upper address bits # Upper address bits
for bit in range(self.row_addr_size): for bit in range(self.row_addr_size):
self.copy_layout_pin(self.row_addr_dff_insts[port], "din_{}".format(bit),"addr{0}[{1}]".format(port,bit+self.col_addr_size)) self.copy_layout_pin(self.row_addr_dff_insts[port],
"din_{}".format(bit),
"addr{0}[{1}]".format(port, bit + self.col_addr_size))
if port in self.write_ports: if port in self.write_ports:
for bit in range(self.word_size): for bit in range(self.word_size):
self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "din{0}[{1}]".format(port,bit)) self.copy_layout_pin(self.data_dff_insts[port],
"din_{}".format(bit),
"din{0}[{1}]".format(port, bit))
if self.write_size: if self.write_size:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port,bit)) self.copy_layout_pin(self.wmask_dff_insts[port],
"din_{}".format(bit),
"wmask{0}[{1}]".format(port, bit))
def route_layout(self): def route_layout(self):
""" Route a single bank SRAM """ """ Route a single bank SRAM """
@ -255,13 +263,15 @@ class sram_1bank(sram_base):
offset=clk_steiner_pos) offset=clk_steiner_pos)
# Note, the via to the control logic is taken care of above # Note, the via to the control logic is taken care of above
self.add_wire(("m3","via2","m2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos]) self.add_wire(("m3", "via2", "m2"),
[row_addr_clk_pos, mid1_pos, clk_steiner_pos])
if self.col_addr_dff: if self.col_addr_dff:
dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk")
dff_clk_pos = dff_clk_pin.center() dff_clk_pos = dff_clk_pin.center()
mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y)
self.add_wire(("m3","via2","m2"),[dff_clk_pos, mid_pos, clk_steiner_pos]) self.add_wire(("m3", "via2", "m2"),
[dff_clk_pos, mid_pos, clk_steiner_pos])
if port in self.write_ports: if port in self.write_ports:
data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
@ -269,8 +279,11 @@ class sram_1bank(sram_base):
mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y)
# In some designs, the steiner via will be too close to the mid_pos via # In some designs, the steiner via will be too close to the mid_pos via
# so make the wire as wide as the contacts # so make the wire as wide as the contacts
self.add_path("m2",[mid_pos, clk_steiner_pos], width=max(m2_via.width,m2_via.height)) self.add_path("m2",
self.add_wire(("m3","via2","m2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) [mid_pos, clk_steiner_pos],
width=max(m2_via.width, m2_via.height))
self.add_wire(("m3", "via2", "m2"),
[data_dff_clk_pos, mid_pos, clk_steiner_pos])
if self.write_size: if self.write_size:
wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk") wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk")
@ -281,7 +294,6 @@ class sram_1bank(sram_base):
self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height)) self.add_path("m2", [mid_pos, clk_steiner_pos], width=max(m2_via.width, m2_via.height))
self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos]) self.add_wire(("m3", "via2", "m2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos])
def route_control_logic(self): def route_control_logic(self):
""" Route the control logic pins that are not inputs """ """ Route the control logic pins that are not inputs """
@ -300,7 +312,6 @@ class sram_1bank(sram_base):
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
self.connect_vbus_m2m3(src_pin, dest_pin) self.connect_vbus_m2m3(src_pin, dest_pin)
def route_row_addr_dff(self): def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """ """ Connect the output of the row flops to the bank pins """
for port in self.all_ports: for port in self.all_ports:
@ -312,7 +323,8 @@ class sram_1bank(sram_base):
flop_pos = flop_pin.center() flop_pos = flop_pin.center()
bank_pos = bank_pin.center() bank_pos = bank_pin.center()
mid_pos = vector(bank_pos.x, flop_pos.y) mid_pos = vector(bank_pos.x, flop_pos.y)
self.add_wire(("m3","via2","m2"),[flop_pos, mid_pos,bank_pos]) self.add_wire(("m3", "via2", "m2"),
[flop_pos, mid_pos, bank_pos])
self.add_via_center(layers=self.m2_stack, self.add_via_center(layers=self.m2_stack,
offset=flop_pos) offset=flop_pos)
@ -339,7 +351,6 @@ class sram_1bank(sram_base):
data_bank_map = zip(bank_names, bus_names) data_bank_map = zip(bank_names, bus_names)
self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets) self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
def route_data_dff(self): def route_data_dff(self):
""" Connect the output of the data flops to the write driver """ """ Connect the output of the data flops to the write driver """
# This is where the channel will start (y-dimension at least) # This is where the channel will start (y-dimension at least)
@ -416,13 +427,11 @@ class sram_1bank(sram_base):
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=offset_pin) offset=offset_pin)
route_map = list(zip(bank_pins, dff_pins)) route_map = list(zip(bank_pins, dff_pins))
self.create_horizontal_channel_route(netlist=route_map, self.create_horizontal_channel_route(netlist=route_map,
offset=offset, offset=offset,
layer_stack=self.m1_stack) layer_stack=self.m1_stack)
def add_lvs_correspondence_points(self): def add_lvs_correspondence_points(self):
""" """
This adds some points for easier debugging if LVS goes wrong. This adds some points for easier debugging if LVS goes wrong.
@ -469,10 +478,10 @@ class sram_1bank(sram_base):
control_conns = self.get_conns(self.control_logic_insts[port]) control_conns = self.get_conns(self.control_logic_insts[port])
# Sanity checks # Sanity checks
if sen_name not in control_conns: if sen_name not in control_conns:
debug.error("Signal={} not contained in control logic connections={}"\ debug.error("Signal={} not contained in control logic connections={}".format(sen_name,
.format(sen_name, control_conns)) control_conns))
if sen_name in self.pins: if sen_name in self.pins:
debug.error("Internal signal={} contained in port list. Name defined by the parent.") debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name))
return "X{}.{}".format(sram_name, sen_name) return "X{}.{}".format(sram_name, sen_name)
def get_cell_name(self, inst_name, row, col): def get_cell_name(self, inst_name, row, col):