mirror of https://github.com/VLSIDA/OpenRAM.git
Add nwell/pwell tap test
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34c9b3a0a5
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5aed893725
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@ -21,7 +21,7 @@ class contact_test(openram_test):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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from tech import poly_stack, beol_stacks
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from tech import active_stack, poly_stack, beol_stacks
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# Don't do active because of nwell contact rules
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# Don't do active because of nwell contact rules
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# Don't do metal3 because of min area rules
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# Don't do metal3 because of min area rules
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@ -67,6 +67,25 @@ class contact_test(openram_test):
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c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(3, 3))
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c = factory.create(module_type="contact", layer_stack=layer_stack, dimensions=(3, 3))
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self.local_drc_check(c)
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self.local_drc_check(c)
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# Test the well taps
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# check vertical array with one in the middle and two ends
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layer_stack = active_stack
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stack_name = ":".join(map(str, layer_stack))
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debug.info(2, "1 x 1 {} nwell".format(stack_name))
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c = factory.create(module_type="contact",
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layer_stack=layer_stack,
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implant_type="n",
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well_type="n")
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self.local_drc_check(c)
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debug.info(2, "1 x 1 {} pwell".format(stack_name))
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c = factory.create(module_type="contact",
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layer_stack=layer_stack,
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implant_type="p",
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well_type="p")
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self.local_drc_check(c)
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globals.end_openram()
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globals.end_openram()
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