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Change how lists of BLs and WLs are named and organized for proper connection between these modules

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samuelkcrow
2022-10-24 20:08:13 -07:00
parent 55d89fbae8
commit 5a82c45a33
2 changed files with 54 additions and 42 deletions
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compiler/modules/replica_bitcell_array.py
+28 -23
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@@ -159,44 +159,49 @@ class replica_bitcell_array(bitcell_base_array):
# Make a flat list too
self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
self.bitline_names = self.bitcell_array.bitline_names
self.bitcell_bitline_names = self.bitcell_array.bitline_names
# Make a flat list too
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
self.all_bitcell_bitline_names = [x for sl in zip(*self.bitcell_bitline_names) for x in sl]
self.all_bitline_names = []
for port in self.left_rbl:
self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
self.add_pin_list(self.all_bitline_names, "INOUT")
self.all_bitline_names.extend(self.rbl_bitline_names[port])
self.all_bitline_names.extend(self.all_bitcell_bitline_names)
for port in self.right_rbl:
self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
self.all_bitline_names.extend(self.rbl_bitline_names[port])
self.add_pin_list(self.all_bitline_names, "INOUT")
def add_wordline_pins(self):
# Wordlines to be grounded by capped_bitcell_array
self.gnd_wordline_names = []
# Unused wordlines are connected to ground at the next level of hierarchy
self.unused_wordline_names = []
for port in self.all_ports:
for bit in self.all_ports:
self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
if bit != port:
self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
self.unused_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
self.wordline_names = self.bitcell_array.wordline_names
self.all_wordline_names = self.bitcell_array.all_wordline_names
self.all_bitcell_wordline_names = self.bitcell_array.all_wordline_names
# All wordlines including dummy and RBL
self.replica_array_wordline_names = []
# All wordlines including RBL
self.all_wordline_names = []
for bit in range(self.rbl[0]):
self.replica_array_wordline_names.extend([x for x in self.rbl_wordline_names[bit]])
self.replica_array_wordline_names.extend(self.all_wordline_names)
self.all_wordline_names.extend(self.rbl_wordline_names[bit])
self.all_wordline_names.extend(self.all_bitcell_wordline_names)
for bit in range(self.rbl[1]):
self.replica_array_wordline_names.extend([x for x in self.rbl_wordline_names[self.rbl[0] + bit]])
self.all_wordline_names.extend(self.rbl_wordline_names[self.rbl[0] + bit])
self.used_wordline_names = []
for port in range(self.rbl[0]):
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
self.add_pin_list(self.all_wordline_names, "INPUT")
self.used_wordline_names.append(self.rbl_wordline_names[port][port])
self.used_wordline_names.extend(self.all_bitcell_wordline_names)
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
self.used_wordline_names.append(self.rbl_wordline_names[port][port])
self.add_pin_list(self.all_wordline_names, "INPUT")
def create_instances(self):
""" Create the module instances used in this design """
@@ -205,7 +210,7 @@ class replica_bitcell_array(bitcell_base_array):
# Main array
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
mod=self.bitcell_array)
self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
self.connect_inst(self.all_bitcell_bitline_names + self.all_bitcell_wordline_names + self.supplies)
# Replica columns
self.replica_col_insts = []
@@ -213,7 +218,7 @@ class replica_bitcell_array(bitcell_base_array):
if port in self.rbls:
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
mod=self.replica_columns[port]))
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
self.connect_inst(self.rbl_bitline_names[port] + self.all_wordline_names + self.supplies)
else:
self.replica_col_insts.append(None)
@@ -223,7 +228,7 @@ class replica_bitcell_array(bitcell_base_array):
for port in self.all_ports:
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
mod=self.dummy_row))
self.connect_inst(self.all_bitline_names + [x for x in self.rbl_wordline_names[port]] + self.supplies)
self.connect_inst(self.all_bitcell_bitline_names + self.rbl_wordline_names[port] + self.supplies)
def create_layout(self):
@@ -331,7 +336,7 @@ class replica_bitcell_array(bitcell_base_array):
# All wordlines
# Main array wl and bl/br
for pin_name in self.all_wordline_names:
for pin_name in self.all_bitcell_wordline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list:
self.add_layout_pin(text=pin_name,
@@ -351,7 +356,7 @@ class replica_bitcell_array(bitcell_base_array):
width=self.width,
height=pin.height())
for pin_name in self.all_bitline_names:
for pin_name in self.all_bitcell_bitline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list:
self.add_layout_pin(text=pin_name,