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Fix all libs to have pin indices

This commit is contained in:
Matt Guthaus 2019-02-22 17:40:49 -08:00
parent 583dc4410b
commit 599e5457a0
4 changed files with 12 additions and 12 deletions
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6
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0; address : ADDR0;
clocked_on : clk0; clocked_on : clk0;
} }
pin(DIN0){ pin(DIN0[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){ memory_read(){
address : ADDR0; address : ADDR0;
} }
pin(DOUT0){ pin(DOUT0[1:0]){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
max_transition : 0.04; max_transition : 0.04;
pin(ADDR0){ pin(ADDR0[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";

6
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0; address : ADDR0;
clocked_on : clk0; clocked_on : clk0;
} }
pin(DIN0){ pin(DIN0[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){ memory_read(){
address : ADDR0; address : ADDR0;
} }
pin(DOUT0){ pin(DOUT0[1:0]){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;
max_transition : 0.04; max_transition : 0.04;
pin(ADDR0){ pin(ADDR0[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";

6
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0; address : ADDR0;
clocked_on : clk0; clocked_on : clk0;
} }
pin(DIN0){ pin(DIN0[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){ memory_read(){
address : ADDR0; address : ADDR0;
} }
pin(DOUT0){ pin(DOUT0[1:0]){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
max_transition : 0.4; max_transition : 0.4;
pin(ADDR0){ pin(ADDR0[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";

6
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0; address : ADDR0;
clocked_on : clk0; clocked_on : clk0;
} }
pin(DIN0){ pin(DIN0[1:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){ memory_read(){
address : ADDR0; address : ADDR0;
} }
pin(DOUT0){ pin(DOUT0[1:0]){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;
max_transition : 0.4; max_transition : 0.4;
pin(ADDR0){ pin(ADDR0[3:0]){
timing(){ timing(){
timing_type : setup_rising; timing_type : setup_rising;
related_pin : "clk0"; related_pin : "clk0";