mirror of https://github.com/VLSIDA/OpenRAM.git
Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message.
This commit is contained in:
parent
acf3fe8376
commit
590f6e01d1
|
|
@ -364,7 +364,7 @@ class delay():
|
|||
for slew in slews:
|
||||
for load in loads:
|
||||
(success, delay1, slew1, delay0, slew0) = self.run_simulation(feasible_period, load, slew)
|
||||
debug.check(success,"Couldn't run a simulation properly.\n")
|
||||
debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(slew,load))
|
||||
LH_delay.append(delay1)
|
||||
HL_delay.append(delay0)
|
||||
LH_slew.append(slew1)
|
||||
|
|
|
|||
|
|
@ -275,7 +275,7 @@ class control_logic(design.design):
|
|||
mod=self.nand2,
|
||||
offset=self.tri_en_bar_offset,
|
||||
mirror="MX")
|
||||
self.connect_inst(["oe", "clk_bar", "tri_en_bar", "vdd", "gnd"])
|
||||
self.connect_inst(["clk_bar", "oe", "tri_en_bar", "vdd", "gnd"])
|
||||
x_off += self.nand2.width
|
||||
|
||||
x_off += self.inv1.width + self.cell_gap
|
||||
|
|
|
|||
|
|
@ -24,8 +24,7 @@ class timing_sram_test(openram_test):
|
|||
reload(characterizer)
|
||||
from characterizer import delay
|
||||
if not OPTS.spice_exe:
|
||||
self.error("Could not find {} simulator.".format(OPTS.spice_name))
|
||||
self.assertTrue(OPTS.spice_exe)
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
import sram
|
||||
|
||||
|
|
|
|||
|
|
@ -24,8 +24,7 @@ class timing_setup_test(openram_test):
|
|||
reload(characterizer)
|
||||
from characterizer import setup_hold
|
||||
if not OPTS.spice_exe:
|
||||
self.error("Could not find {} simulator.".format(OPTS.spice_name))
|
||||
self.assertTrue(OPTS.spice_exe)
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
|
||||
import sram
|
||||
|
|
|
|||
|
|
@ -24,8 +24,7 @@ class timing_sram_test(openram_test):
|
|||
reload(characterizer)
|
||||
from characterizer import delay
|
||||
if not OPTS.spice_exe:
|
||||
self.error("Could not find {} simulator.".format(OPTS.spice_name))
|
||||
self.assertTrue(OPTS.spice_exe)
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
import sram
|
||||
|
||||
|
|
|
|||
|
|
@ -24,8 +24,7 @@ class timing_setup_test(openram_test):
|
|||
reload(characterizer)
|
||||
from characterizer import setup_hold
|
||||
if not OPTS.spice_exe:
|
||||
self.error("Could not find {} simulator.".format(OPTS.spice_name))
|
||||
self.assertTrue(OPTS.spice_exe)
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
import sram
|
||||
import tech
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ class lib_test(openram_test):
|
|||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.check_lvsdrc = False
|
||||
OPTS.spice_name="hspice"
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.trim_netlist = True
|
||||
import characterizer
|
||||
reload(characterizer)
|
||||
from characterizer import lib
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -129,7 +129,7 @@ class openram_test(unittest.TestCase):
|
|||
if len(b1_floats)!=len(b2_floats):
|
||||
self.fail("MISMATCH Length {0} != {1}".format(len(b1_floats),len(b2_floats)))
|
||||
for (f1,f2) in zip(b1_floats,b2_floats):
|
||||
if not relative_compare(float(f1),float(f2),error_tolerance):
|
||||
if not self.relative_compare(float(f1),float(f2),error_tolerance):
|
||||
self.fail("MISMATCH Float {0} != {1}".format(f1,f2))
|
||||
|
||||
if not b1 and not b2:
|
||||
|
|
|
|||
Loading…
Reference in New Issue