luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix disconnected spare_wen_0_0

This commit is contained in:
mrg 2021-06-21 17:36:20 -07:00
parent bb1ac1a38e
commit 58f8c66020
1 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
compiler/sram/sram_base.py
View File

@ -701,13 +701,9 @@ class sram_base(design, verilog, lef):
# inputs, outputs/output/bar # inputs, outputs/output/bar
inputs = [] inputs = []
outputs = [] outputs = []
if self.num_spare_cols == 1: for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}".format(port)) inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}".format(port)) outputs.append("bank_spare_wen{}_{}".format(port, bit))
else:
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)