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Fix disconnected spare_wen_0_0

This commit is contained in:
mrg 2021-06-21 17:36:20 -07:00
parent bb1ac1a38e
commit 58f8c66020
1 changed files with 3 additions and 7 deletions
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4
compiler/sram/sram_base.py
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@ -701,10 +701,6 @@ class sram_base(design, verilog, lef):
# inputs, outputs/output/bar # inputs, outputs/output/bar
inputs = [] inputs = []
outputs = [] outputs = []
if self.num_spare_cols == 1:
inputs.append("spare_wen{}".format(port))
outputs.append("bank_spare_wen{}".format(port))
else:
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit)) inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit))